A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Aug 12, 2025 - SystemVerilog
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vlsi-design
Here are 9 public repositories matching this topic...
Spiking Neural Network Accelerator
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May 18, 2022 - SystemVerilog
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
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May 9, 2022 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Jun 19, 2025 - SystemVerilog
5-stage-Pipeline-CPU with AXI bus
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Nov 7, 2024 - SystemVerilog
Verilog-Training-5-stage-Pipeline-CPU
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Jan 26, 2025 - SystemVerilog
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
asic verification verilog systemverilog soc sv vlsi-design systemverilog-examples systemverilog-problems
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Mar 31, 2023 - SystemVerilog
SystemVerilog verification of I2C interface
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Dec 12, 2023 - SystemVerilog
AMBA AXI4 design & verification flow in SystemVerilog with UVM 1.2. Includes master/slave RTL & golden models, assertions, functional & code coverage, FSMs, active master & passive slave agents, cross-platform run scripts, and waveform/report generation for protocol-compliant verification.
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Aug 13, 2025 - SystemVerilog
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