verilog-hdl
Here are 427 public repositories matching this topic...
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Apr 30, 2024 - Verilog
High throughput JPEG decoder in Verilog for FPGA
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Mar 5, 2022 - Verilog
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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Jun 20, 2024 - Verilog
A simple implementation of a UART modem in Verilog.
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Nov 10, 2021 - Verilog
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
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Jan 29, 2024 - Verilog
5-stage pipelined 32-bit MIPS microprocessor in Verilog
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Apr 3, 2020 - Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
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Jul 31, 2022 - Verilog
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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Dec 29, 2024 - Verilog
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
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Mar 21, 2021 - Verilog
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
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May 26, 2019 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
Gigabit Ethernet UDP communication driver
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Jul 26, 2019 - Verilog
FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch
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Jun 30, 2025 - Verilog
Implementing Different Adder Structures in Verilog
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Sep 3, 2019 - Verilog
FPGA implementation of deflate (de)compress RFC 1950/1951
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May 2, 2019 - Verilog
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
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Nov 25, 2020 - Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
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Nov 30, 2022 - Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
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Mar 15, 2024 - Verilog
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