This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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verification-code
Here are 4 public repositories matching this topic...
This Repository contains the verification of a Synchronous FIFO design using SystemVerilog and SystemVerilogAssertions
systemverilog fifo verification-methodologies verification-code digitalverification systemverilog-assertions
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Jan 31, 2025 - SystemVerilog
EE-599f SoC SystemVerilog Final Project
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Apr 21, 2022 - SystemVerilog
Coverage, Assertions, Randomizations, Mailbox, Semaphores, DPI and OOP: Inheritance, Polymorphism, Virtual methods
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Mar 8, 2024 - SystemVerilog
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