DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

A Python library for working with logic networks, synthesis, and optimization.

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

Awesome machine learning for logic synthesis

The SubXPAT approximate logic synthesis framework

Electronic design automation for Minecraft

(WIP) Training an RL model to produce synthesis recipes for logic optimization.

An implementation of LUT-Net learning procedure

An implementation of binary decision tree with fringe-features extraction.

To generate an electrical circuit from the given input and output boolean values.

CELLO - Cell Genetic Circuit Design Automation. Python code built from the ground up, which branched off into the repositories Cello-V3-Core and UCFormatter.

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization

Code repository for the IWLS 2021 Programming Contest