DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
-
Updated
May 18, 2023 - Python
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
A Python library for working with logic networks, synthesis, and optimization.
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Awesome machine learning for logic synthesis
Electronic design automation for Minecraft
The SubXPAT approximate logic synthesis framework
An implementation of LUT-Net learning procedure
(WIP) Training an RL model to produce synthesis recipes for logic optimization.
An implementation of binary decision tree with fringe-features extraction.
To generate an electrical circuit from the given input and output boolean values.
Code repository for the IWLS 2021 Programming Contest
CELLO - Cell Genetic Circuit Design Automation. Python code built from the ground up, which branched off into the repositories Cello-V3-Core and UCFormatter.
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization
Add a description, image, and links to the logic-synthesis topic page so that developers can more easily learn about it.
To associate your repository with the logic-synthesis topic, visit your repo's landing page and select "manage topics."