IceChips is a library of all common discrete logic devices in Verilog
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Updated
Nov 20, 2024 - Verilog
IceChips is a library of all common discrete logic devices in Verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology, which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Tool for creating synchronous models and behavioral specifications for asynchronous circuits
A Chinese Klotski game played on Xilinx FPGA
同济大学CS《数字逻辑》大作业: 车床仿真系统TongJi University CS digital logic assignment: lathe simulation system
An 8085-based Computer
Projects from a second-year computer engineering course on digital logic (written in Verilog)
Design and simulation of digital logic circuits using Verilog
EECS207001
FlappyBird on VGA Display using Verilog
Professional IEEE 1149.1 (JTAG), 1500, and 1687 network implementation with comprehensive verification, cross-platform build system, and complete documentation. Production-ready codebase for digital test infrastructure.
Sogang University Computer Science Lab 2 assignments and projects(2024)
A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning journey using open-source tools.
A collection of VLSI and Verilog-based hardware design projects.
11020EECS101002
Creating A Configurable Multifunction Logic Gate In Verilog Article Resources
implementation of a machine executes simple operations in general built-in registers in Verilog
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