computerarchitecture

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CPU Labs

This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented

fpga verilog uart volunteering computerarchitecture

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

Solutions of Computer Architecture Labs using verilog.

encoder verilog computerarchitecture registerfile

Contains the codes and reports that were done as a part of the CS2310 and CS2610: Computer Architecture

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