A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
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May 20, 2022 - Verilog
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computer-architecture
Here are 232 public repositories matching this topic...
5-stage pipelined 32-bit MIPS microprocessor in Verilog
verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project
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Apr 3, 2020 - Verilog
RISC-V Embedded Processor for Approximate Computing
cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design
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May 30, 2025 - Verilog
Verilog implementation of multi-stage 32-bit RISC-V processor
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Nov 2, 2020 - Verilog
A computer system containing CPU, OS and Compiler under MIPS architecture.
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Sep 9, 2021 - Verilog
This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum
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Nov 27, 2021 - Verilog
Hardware accelerator for convolutional neural networks
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Aug 9, 2022 - Verilog
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
assembly assembler verilog computer-architecture instruction-set-architecture computer-organization hardware-description-language processor-design single-cycle-processor
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Dec 7, 2024 - Verilog
💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
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Jul 5, 2020 - Verilog
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWa…
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Oct 31, 2021 - Verilog
RISC V core implementation using Verilog.
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Mar 27, 2021 - Verilog
16 bit CPU created in Vivado with Verilog
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Jun 30, 2022 - Verilog
Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
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Nov 17, 2017 - Verilog
Single Cycle CPU using the RV32I Base Instruction set
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Jul 15, 2023 - Verilog
This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.
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May 6, 2025 - Verilog
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
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Jan 4, 2020 - Verilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor
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Feb 19, 2025 - Verilog
Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.
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Jul 15, 2024 - Verilog
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator
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May 8, 2021 - Verilog
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