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[wasm] Fix build failure due to lack of _Float16 support #72891
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kateinoigakukun
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Apr 9, 2024
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Why does that happen? Surely
Float32
can represent at least as manyNaN
values asFloat16
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Yes,
Float32
can represent allNaN
patterns that can be representable asFloat16
. However, sNaN values are converted to qNaN while roundtrippingFloat16
->Float32
->Float16
for argument passing on platforms that don't have native Float16 support.The actual conversion happens in a builtin that is used by
swift_float16ToString
to truncateFloat32
->Float16
: https://github.com/llvm/llvm-project/blob/1107b47dcd145518c7b811bf10e2b848782b0478/compiler-rt/lib/builtins/fp_trunc_impl.inc#L111Therefore the check fails on WebAssembly unfortunatley.
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Here is a minimum reproducible code for the implicit bit pattern change.
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I wouldn't claim to be an expert (@stephentyrone is the man to talk to here), but that sounds like a bug.
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I'm not an expert here too, but as far as I investigated, the root cause seems the LLVM default lowering behavior for
half
type that passes aroundhalf
type asfloat
. Due to the LLVM lowering,Float16
is represented asf32
at Wasm level and sNaN values are converted to qNaN while extendingbitPattern
ofFloat16(bitPattern:)
toFloat32
. (I said the conversion happens while roundtripping f16 -> f32 -> f16 in printing, but I found it also happens more primitiveFloat16(bitPattern:)
casting)I feel changing NaN payload pattern while bit-width extension seems not a strange behavior. According to x64 manual, some instructions that convert float to double (e.g.
CVTSS2SD
) return qNaN when the source is sNaN1. And also Wasm does similar canonicalization for fp operations including truncation and promotion against f32/f642.If we really want to guarantee bitwise equivalence between the given bitPattern and the resulted Float16's bitPattern, we have three options:
__extendhfsf2
to hold NaN payload patternssoftPromoteHalfType
for Wasm targets to pass aroundhalf
type asi16
at Wasm levelIRGen
to usei16
to representBuiltin.FPIEEE16
instead ofhalf
at LLVM IR level for such archsBut I'm not sure it's worth paying such effort only for sNaN Float16 on platforms without native support, but I'd like to hear @stephentyrone 's opinion.
Footnotes
Table D-11. CVTPS2PD and CVTSS2SD, Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 ↩
https://webassembly.github.io/spec/core/exec/numerics.html#nan-propagation ↩
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It's the correct behavior. A conversion is required to silence NaNs per 754.