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Merged
merged 1 commit into from
Nov 13, 2024
Merged

chore: update to STM32CubeCLT version 1.16.0 #1

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67,357 changes: 67,357 additions & 0 deletions svd/STM32C0xx/STM32C071.svd
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2 changes: 1 addition & 1 deletion svd/STM32CubeCLT.version
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@@ -1 +1 @@
1.15.1
1.16.0
49 changes: 48 additions & 1 deletion svd/STM32G0xx/STM32G030.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G030</name>
<version>1.6</version>
<version>1.7</version>
<description>STM32G030</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -3968,6 +3968,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur
</field>
</fields>
</register>
<register>
<name>ECCR2</name>
<displayName>ECCR2</displayName>
<description>Flash ECC register 2</description>
<addressOffset>0x01C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>ECC fail for Corrected ECC Error or
Double ECC Error in info block</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECC correction interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
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4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G031.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G031</name>
<version>1.6</version>
<version>1.7</version>
<description>STM32G031</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
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4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G041.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G041</name>
<version>1.5</version>
<version>1.6</version>
<description>STM32G041</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -608,7 +608,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
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49 changes: 48 additions & 1 deletion svd/STM32G0xx/STM32G050.svd
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Expand Up @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G050</name>
<version>1.3</version>
<version>1.4</version>
<description>STM32G050</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -11076,6 +11076,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
</field>
</fields>
</register>
<register>
<name>ECCR2</name>
<displayName>ECCR2</displayName>
<description>Flash ECC register 2</description>
<addressOffset>0x01C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>ECC fail for Corrected ECC Error or
Double ECC Error in info block</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECC correction interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
Expand Down
6 changes: 3 additions & 3 deletions svd/STM32G0xx/STM32G051.svd
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Expand Up @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G051</name>
<version>1.4</version>
<version>1.5</version>
<description>STM32G051</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -4074,7 +4074,7 @@ This bit is set by software and cleared by a system reset. It locks the whole co
</register>
<register>
<name>COMP3_CSR</name>
<displayName>COMP2_CSR</displayName>
<displayName>COMP3_CSR</displayName>
<description>Comparator 2 control and status register </description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
Expand Down Expand Up @@ -12706,7 +12706,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
Expand Down
4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G061.svd
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Expand Up @@ -18,7 +18,7 @@ Copyright (c) 2024 STMicroelectronics.
-->
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G061</name>
<version>1.4</version>
<version>1.5</version>
<description>STM32G061</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -12772,7 +12772,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
Expand Down
49 changes: 48 additions & 1 deletion svd/STM32G0xx/STM32G070.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G070</name>
<version>1.9</version>
<version>2.0</version>
<description>STM32G070</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -4049,6 +4049,53 @@ Note: The software is allowed to write this bit only when ADSTART=0 (which ensur
</field>
</fields>
</register>
<register>
<name>ECCR2</name>
<displayName>ECCR2</displayName>
<description>Flash ECC register 2</description>
<addressOffset>0x01C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>ECC fail for Corrected ECC Error or
Double ECC Error in info block</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECC correction interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
Expand Down
4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G071.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G071</name>
<version>2.5</version>
<version>2.6</version>
<description>STM32G071</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
Expand Down
4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G081.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G081</name>
<version>1.8</version>
<version>1.9</version>
<description>STM32G081</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -689,7 +689,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
Expand Down
51 changes: 49 additions & 2 deletions svd/STM32G0xx/STM32G0B0.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G0B0</name>
<version>1.6</version>
<version>1.7</version>
<description>STM32G0B0</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -10441,6 +10441,53 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
</field>
</fields>
</register>
<register>
<name>ECCR2</name>
<displayName>ECCR2</displayName>
<description>Flash ECC register 2</description>
<addressOffset>0x01C</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SYSF_ECC</name>
<description>ECC fail for Corrected ECC Error or
Double ECC Error in info block</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ECCIE</name>
<description>ECC correction interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCC</name>
<description>ECC correction</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ECCD</name>
<description>ECC detection</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>OPTR</name>
<displayName>OPTR</displayName>
Expand Down Expand Up @@ -10532,7 +10579,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</register>
<register>
<name>WRP1AR</name>
<displayName>WRP1AR</displayName>
Expand Down
4 changes: 2 additions & 2 deletions svd/STM32G0xx/STM32G0B1.svd
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Expand Up @@ -20,7 +20,7 @@ Copyright (c) 2024 STMicroelectronics.
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32G0B1</name>
<version>1.8</version>
<version>1.9</version>
<description>STM32G0B1</description>
<cpu>
<name>CM0</name>
Expand Down Expand Up @@ -16111,7 +16111,7 @@ These are protected write (P) bits, which means that write access by the bits is
<name>ADDR_ECC</name>
<description>ECC fail address</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<bitWidth>14</bitWidth>
<access>read-only</access>
</field>
<field>
Expand Down
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