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ARM: Only allow using d16-d31 with asm! when supported by the target #94339

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Merged
merged 1 commit into from
Mar 4, 2022
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ARM: Only allow using d16-d31 with asm! when supported by the target #94339

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1 change: 1 addition & 0 deletions compiler/rustc_codegen_ssa/src/target_features.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ const ARM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
// #[target_feature].
("thumb-mode", Some(sym::arm_target_feature)),
("thumb2", Some(sym::arm_target_feature)),
("d32", Some(sym::arm_target_feature)),
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Hm, given that these three features seem to be fated to remain unstable, maybe a different feature gate would be warranted for these?

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The 32-bit ARM features are bit of a mess and will need to be reworked anyways before stabilization can be considered.

];

const AARCH64_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
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1 change: 1 addition & 0 deletions compiler/rustc_span/src/symbol.rs
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Expand Up @@ -539,6 +539,7 @@ symbols! {
custom_inner_attributes,
custom_test_frameworks,
d,
d32,
dbg_macro,
dead_code,
dealloc,
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5 changes: 4 additions & 1 deletion compiler/rustc_target/src/asm/arm.rs
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Expand Up @@ -50,9 +50,12 @@ impl ArmInlineAsmRegClass {
match self {
Self::reg => types! { _: I8, I16, I32, F32; },
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; },
Self::dreg | Self::dreg_low16 | Self::dreg_low8 => types! {
Self::dreg_low16 | Self::dreg_low8 => types! {
vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
},
Self::dreg => types! {
d32: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
},
Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! {
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
},
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