Rollup of 6 pull requests

compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs

@@ -2,6 +2,7 @@
 
 use cranelift_codegen::ir::immediates::Offset32;
 use rustc_abi::Endian;
+use rustc_middle::ty::SimdAlign;
 
 use super::*;
 use crate::prelude::*;
@@ -960,6 +961,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
             let ptr_val = ptr.load_scalar(fx);
 
+            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                .unwrap_leaf()
+                .to_simd_alignment();
+
+            let memflags = match alignment {
+                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
+                _ => MemFlags::trusted(),
+            };
+
             for lane_idx in 0..val_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let mask_lane = mask.value_lane(fx, lane_idx).load_scalar(fx);
@@ -972,7 +982,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
 
                 fx.bcx.switch_to_block(if_enabled);
                 let offset = lane_idx as i32 * lane_clif_ty.bytes() as i32;
-                fx.bcx.ins().store(MemFlags::trusted(), val_lane, ptr_val, Offset32::new(offset));
+                fx.bcx.ins().store(memflags, val_lane, ptr_val, Offset32::new(offset));
                 fx.bcx.ins().jump(next, &[]);
 
                 fx.bcx.seal_block(next);
@@ -996,6 +1006,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
             let ret_lane_layout = fx.layout_of(ret_lane_ty);
 
+            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                .unwrap_leaf()
+                .to_simd_alignment();
+
+            let memflags = match alignment {
+                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
+                _ => MemFlags::trusted(),
+            };
+
             for lane_idx in 0..ptr_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let ptr_lane = ptr.value_lane(fx, lane_idx).load_scalar(fx);
@@ -1011,7 +1030,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
                 fx.bcx.seal_block(if_disabled);
 
                 fx.bcx.switch_to_block(if_enabled);
-                let res = fx.bcx.ins().load(lane_clif_ty, MemFlags::trusted(), ptr_lane, 0);
+                let res = fx.bcx.ins().load(lane_clif_ty, memflags, ptr_lane, 0);
                 fx.bcx.ins().jump(next, &[res.into()]);
 
                 fx.bcx.switch_to_block(if_disabled);

compiler/rustc_codegen_llvm/src/back/write.rs

@@ -451,7 +451,7 @@ fn report_inline_asm(
         llvm::DiagnosticLevel::Warning => Level::Warning,
         llvm::DiagnosticLevel::Note | llvm::DiagnosticLevel::Remark => Level::Note,
     };
-    let msg = msg.strip_prefix("error: ").unwrap_or(&msg).to_string();
+    let msg = msg.trim_prefix("error: ").to_string();
     cgcx.diag_emitter.inline_asm_error(span, msg, level, source);
 }
 

compiler/rustc_codegen_llvm/src/intrinsic.rs

@@ -13,7 +13,7 @@ use rustc_hir::def_id::LOCAL_CRATE;
 use rustc_hir::{self as hir};
 use rustc_middle::mir::BinOp;
 use rustc_middle::ty::layout::{FnAbiOf, HasTyCtxt, HasTypingEnv, LayoutOf};
-use rustc_middle::ty::{self, GenericArgsRef, Instance, Ty, TyCtxt, TypingEnv};
+use rustc_middle::ty::{self, GenericArgsRef, Instance, SimdAlign, Ty, TyCtxt, TypingEnv};
 use rustc_middle::{bug, span_bug};
 use rustc_span::{Span, Symbol, sym};
 use rustc_symbol_mangling::{mangle_internal_symbol, symbol_name_for_instance_in_crate};
@@ -1840,15 +1840,32 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
         return Ok(call);
     }
 
+    fn llvm_alignment<'ll, 'tcx>(
+        bx: &mut Builder<'_, 'll, 'tcx>,
+        alignment: SimdAlign,
+        vector_ty: Ty<'tcx>,
+        element_ty: Ty<'tcx>,
+    ) -> u64 {
+        match alignment {
+            SimdAlign::Unaligned => 1,
+            SimdAlign::Element => bx.align_of(element_ty).bytes(),
+            SimdAlign::Vector => bx.align_of(vector_ty).bytes(),
+        }
+    }
+
     if name == sym::simd_masked_load {
-        // simd_masked_load(mask: <N x i{M}>, pointer: *_ T, values: <N x T>) -> <N x T>
+        // simd_masked_load<_, _, _, const ALIGN: SimdAlign>(mask: <N x i{M}>, pointer: *_ T, values: <N x T>) -> <N x T>
         // * N: number of elements in the input vectors
         // * T: type of the element to load
         // * M: any integer width is supported, will be truncated to i1
         // Loads contiguous elements from memory behind `pointer`, but only for
         // those lanes whose `mask` bit is enabled.
         // The memory addresses corresponding to the “off” lanes are not accessed.
 
+        let alignment = fn_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+            .unwrap_leaf()
+            .to_simd_alignment();
+
         // The element type of the "mask" argument must be a signed integer type of any width
         let mask_ty = in_ty;
         let (mask_len, mask_elem) = (in_len, in_elem);
@@ -1905,7 +1922,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
         let mask = vector_mask_to_bitmask(bx, args[0].immediate(), m_elem_bitwidth, mask_len);
 
         // Alignment of T, must be a constant integer value:
-        let alignment = bx.align_of(values_elem).bytes();
+        let alignment = llvm_alignment(bx, alignment, values_ty, values_elem);
 
         let llvm_pointer = bx.type_ptr();
 
@@ -1932,14 +1949,18 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
     }
 
     if name == sym::simd_masked_store {
-        // simd_masked_store(mask: <N x i{M}>, pointer: *mut T, values: <N x T>) -> ()
+        // simd_masked_store<_, _, _, const ALIGN: SimdAlign>(mask: <N x i{M}>, pointer: *mut T, values: <N x T>) -> ()
         // * N: number of elements in the input vectors
         // * T: type of the element to load
         // * M: any integer width is supported, will be truncated to i1
         // Stores contiguous elements to memory behind `pointer`, but only for
         // those lanes whose `mask` bit is enabled.
         // The memory addresses corresponding to the “off” lanes are not accessed.
 
+        let alignment = fn_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+            .unwrap_leaf()
+            .to_simd_alignment();
+
         // The element type of the "mask" argument must be a signed integer type of any width
         let mask_ty = in_ty;
         let (mask_len, mask_elem) = (in_len, in_elem);
@@ -1990,7 +2011,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
         let mask = vector_mask_to_bitmask(bx, args[0].immediate(), m_elem_bitwidth, mask_len);
 
         // Alignment of T, must be a constant integer value:
-        let alignment = bx.align_of(values_elem).bytes();
+        let alignment = llvm_alignment(bx, alignment, values_ty, values_elem);
 
         let llvm_pointer = bx.type_ptr();
 

compiler/rustc_codegen_llvm/src/lib.rs

@@ -17,6 +17,7 @@
 #![feature(macro_derive)]
 #![feature(rustdoc_internals)]
 #![feature(slice_as_array)]
+#![feature(trim_prefix_suffix)]
 #![feature(try_blocks)]
 // tidy-alphabetical-end
 

compiler/rustc_const_eval/src/interpret/intrinsics/simd.rs

@@ -1,16 +1,16 @@
 use either::Either;
-use rustc_abi::Endian;
+use rustc_abi::{BackendRepr, Endian};
 use rustc_apfloat::ieee::{Double, Half, Quad, Single};
 use rustc_apfloat::{Float, Round};
-use rustc_middle::mir::interpret::{InterpErrorKind, UndefinedBehaviorInfo};
-use rustc_middle::ty::FloatTy;
+use rustc_middle::mir::interpret::{InterpErrorKind, Pointer, UndefinedBehaviorInfo};
+use rustc_middle::ty::{FloatTy, SimdAlign};
 use rustc_middle::{bug, err_ub_format, mir, span_bug, throw_unsup_format, ty};
 use rustc_span::{Symbol, sym};
 use tracing::trace;
 
 use super::{
     ImmTy, InterpCx, InterpResult, Machine, MinMax, MulAddType, OpTy, PlaceTy, Provenance, Scalar,
-    Size, interp_ok, throw_ub_format,
+    Size, TyAndLayout, assert_matches, interp_ok, throw_ub_format,
 };
 use crate::interpret::Writeable;
 
@@ -644,6 +644,8 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
                 }
             }
             sym::simd_masked_load => {
+                let dest_layout = dest.layout;
+
                 let (mask, mask_len) = self.project_to_simd(&args[0])?;
                 let ptr = self.read_pointer(&args[1])?;
                 let (default, default_len) = self.project_to_simd(&args[2])?;
@@ -652,6 +654,14 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
                 assert_eq!(dest_len, mask_len);
                 assert_eq!(dest_len, default_len);
 
+                self.check_simd_ptr_alignment(
+                    ptr,
+                    dest_layout,
+                    generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                        .unwrap_leaf()
+                        .to_simd_alignment(),
+                )?;
+
                 for i in 0..dest_len {
                     let mask = self.read_immediate(&self.project_index(&mask, i)?)?;
                     let default = self.read_immediate(&self.project_index(&default, i)?)?;
@@ -660,7 +670,8 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
                     let val = if simd_element_to_bool(mask)? {
                         // Size * u64 is implemented as always checked
                         let ptr = ptr.wrapping_offset(dest.layout.size * i, self);
-                        let place = self.ptr_to_mplace(ptr, dest.layout);
+                        // we have already checked the alignment requirements
+                        let place = self.ptr_to_mplace_unaligned(ptr, dest.layout);
                         self.read_immediate(&place)?
                     } else {
                         default
@@ -675,14 +686,23 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
 
                 assert_eq!(mask_len, vals_len);
 
+                self.check_simd_ptr_alignment(
+                    ptr,
+                    args[2].layout,
+                    generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                        .unwrap_leaf()
+                        .to_simd_alignment(),
+                )?;
+
                 for i in 0..vals_len {
                     let mask = self.read_immediate(&self.project_index(&mask, i)?)?;
                     let val = self.read_immediate(&self.project_index(&vals, i)?)?;
 
                     if simd_element_to_bool(mask)? {
                         // Size * u64 is implemented as always checked
                         let ptr = ptr.wrapping_offset(val.layout.size * i, self);
-                        let place = self.ptr_to_mplace(ptr, val.layout);
+                        // we have already checked the alignment requirements
+                        let place = self.ptr_to_mplace_unaligned(ptr, val.layout);
                         self.write_immediate(*val, &place)?
                     };
                 }
@@ -753,6 +773,30 @@ impl<'tcx, M: Machine<'tcx>> InterpCx<'tcx, M> {
             FloatTy::F128 => self.float_minmax::<Quad>(left, right, op)?,
         })
     }
+
+    fn check_simd_ptr_alignment(
+        &self,
+        ptr: Pointer<Option<M::Provenance>>,
+        vector_layout: TyAndLayout<'tcx>,
+        alignment: SimdAlign,
+    ) -> InterpResult<'tcx> {
+        assert_matches!(vector_layout.backend_repr, BackendRepr::SimdVector { .. });
+
+        let align = match alignment {
+            ty::SimdAlign::Unaligned => {
+                // The pointer is supposed to be unaligned, so no check is required.
+                return interp_ok(());
+            }
+            ty::SimdAlign::Element => {
+                // Take the alignment of the only field, which is an array and therefore has the same
+                // alignment as the element type.
+                vector_layout.field(self, 0).align.abi
+            }
+            ty::SimdAlign::Vector => vector_layout.align.abi,
+        };
+
+        self.check_ptr_align(ptr, align)
+    }
 }
 
 fn simd_bitmask_index(idx: u32, vec_len: u32, endianness: Endian) -> u32 {

compiler/rustc_driver_impl/src/lib.rs

@@ -13,6 +13,7 @@
 #![feature(panic_backtrace_config)]
 #![feature(panic_update_hook)]
 #![feature(rustdoc_internals)]
+#![feature(trim_prefix_suffix)]
 #![feature(try_blocks)]
 // tidy-alphabetical-end
 
@@ -466,7 +467,7 @@ pub enum Compilation {
 fn handle_explain(early_dcx: &EarlyDiagCtxt, registry: Registry, code: &str, color: ColorConfig) {
     // Allow "E0123" or "0123" form.
     let upper_cased_code = code.to_ascii_uppercase();
-    if let Ok(code) = upper_cased_code.strip_prefix('E').unwrap_or(&upper_cased_code).parse::<u32>()
+    if let Ok(code) = upper_cased_code.trim_prefix('E').parse::<u32>()
         && code <= ErrCode::MAX_AS_U32
         && let Ok(description) = registry.try_find_description(ErrCode::from_u32(code))
     {
@@ -1267,7 +1268,7 @@ fn warn_on_confusing_output_filename_flag(
     if let Some(name) = matches.opt_str("o")
         && let Some(suspect) = args.iter().find(|arg| arg.starts_with("-o") && *arg != "-o")
     {
-        let filename = suspect.strip_prefix("-").unwrap_or(suspect);
+        let filename = suspect.trim_prefix("-");
         let optgroups = config::rustc_optgroups();
         let fake_args = ["optimize", "o0", "o1", "o2", "o3", "ofast", "og", "os", "oz"];
 

compiler/rustc_hir_analysis/src/check/intrinsic.rs

@@ -695,8 +695,8 @@ pub(crate) fn check_intrinsic_type(
             (1, 0, vec![param(0), param(0), param(0)], param(0))
         }
         sym::simd_gather => (3, 0, vec![param(0), param(1), param(2)], param(0)),
-        sym::simd_masked_load => (3, 0, vec![param(0), param(1), param(2)], param(2)),
-        sym::simd_masked_store => (3, 0, vec![param(0), param(1), param(2)], tcx.types.unit),
+        sym::simd_masked_load => (3, 1, vec![param(0), param(1), param(2)], param(2)),
+        sym::simd_masked_store => (3, 1, vec![param(0), param(1), param(2)], tcx.types.unit),
         sym::simd_scatter => (3, 0, vec![param(0), param(1), param(2)], tcx.types.unit),
         sym::simd_insert | sym::simd_insert_dyn => {
             (2, 0, vec![param(0), tcx.types.u32, param(1)], param(0))

compiler/rustc_hir_typeck/src/lib.rs

@@ -7,6 +7,7 @@
 #![feature(iter_intersperse)]
 #![feature(iter_order_by)]
 #![feature(never_type)]
+#![feature(trim_prefix_suffix)]
 // tidy-alphabetical-end
 
 mod _match;

compiler/rustc_hir_typeck/src/method/suggest.rs

@@ -2551,7 +2551,7 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> {
 
                     // If this is a floating point literal that ends with '.',
                     // get rid of it to stop this from becoming a member access.
-                    let snippet = snippet.strip_suffix('.').unwrap_or(&snippet);
+                    let snippet = snippet.trim_suffix('.');
                     err.span_suggestion(
                         lit.span,
                         format!(

compiler/rustc_index/Cargo.toml

@@ -8,7 +8,7 @@ edition = "2024"
 rustc_index_macros = { path = "../rustc_index_macros" }
 rustc_macros = { path = "../rustc_macros", optional = true }
 rustc_serialize = { path = "../rustc_serialize", optional = true }
-smallvec = "1.8.1"
+smallvec = { version = "1.8.1", optional = true }
 # tidy-alphabetical-end
 
 [features]
@@ -17,6 +17,7 @@ default = ["nightly"]
 nightly = [
     "dep:rustc_macros",
     "dep:rustc_serialize",
+    "dep:smallvec",
     "rustc_index_macros/nightly",
 ]
 rustc_randomized_layouts = []

compiler/rustc_middle/src/ty/consts/int.rs

@@ -39,6 +39,15 @@ pub enum AtomicOrdering {
     SeqCst = 4,
 }
 
+/// An enum to represent the compiler-side view of `intrinsics::simd::SimdAlign`.
+#[derive(Debug, Copy, Clone)]
+pub enum SimdAlign {
+    // These values must match `intrinsics::simd::SimdAlign`!
+    Unaligned = 0,
+    Element = 1,
+    Vector = 2,
+}
+
 impl std::fmt::Debug for ConstInt {
     fn fmt(&self, fmt: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
         let Self { int, signed, is_ptr_sized_integral } = *self;
@@ -350,6 +359,21 @@ impl ScalarInt {
         }
     }
 
+    #[inline]
+    pub fn to_simd_alignment(self) -> SimdAlign {
+        use SimdAlign::*;
+        let val = self.to_u32();
+        if val == Unaligned as u32 {
+            Unaligned
+        } else if val == Element as u32 {
+            Element
+        } else if val == Vector as u32 {
+            Vector
+        } else {
+            panic!("not a valid simd alignment")
+        }
+    }
+
     /// Converts the `ScalarInt` to `bool`.
     /// Panics if the `size` of the `ScalarInt` is not equal to 1 byte.
     /// Errors if it is not a valid `bool`.

compiler/rustc_middle/src/ty/mod.rs

@@ -74,7 +74,7 @@ pub use self::closure::{
 };
 pub use self::consts::{
     AnonConstKind, AtomicOrdering, Const, ConstInt, ConstKind, ConstToValTreeResult, Expr,
-    ExprKind, ScalarInt, UnevaluatedConst, ValTree, ValTreeKind, Value,
+    ExprKind, ScalarInt, SimdAlign, UnevaluatedConst, ValTree, ValTreeKind, Value,
 };
 pub use self::context::{
     CtxtInterners, CurrentGcx, Feed, FreeRegionInfo, GlobalCtxt, Lift, TyCtxt, TyCtxtFeed, tls,

compiler/rustc_resolve/src/late/diagnostics.rs

@@ -2608,7 +2608,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
             let (span, text) = match path.segments.first() {
                 Some(seg) if let Some(name) = seg.ident.as_str().strip_prefix("let") => {
                     // a special case for #117894
-                    let name = name.strip_prefix('_').unwrap_or(name);
+                    let name = name.trim_prefix('_');
                     (ident_span, format!("let {name}"))
                 }
                 _ => (ident_span.shrink_to_lo(), "let ".to_string()),