Skip to content
7 changes: 4 additions & 3 deletions tests/assembly/dwarf-mixed-versions-lto.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
// This test ensures that if LTO occurs between crates with different DWARF versions, we
// will choose the highest DWARF version for the final binary. This matches Clang's behavior.
// Note: `.2byte` directive is used on MIPS.
// Note: `.half` directive is used on RISC-V.

//@ only-linux
//@ aux-build:dwarf-mixed-versions-lto-aux.rs
Expand All @@ -15,6 +16,6 @@ fn main() {
}

// CHECK: .section .debug_info
// CHECK-NOT: {{\.(short|hword|2byte)}} 2
// CHECK-NOT: {{\.(short|hword|2byte)}} 4
// CHECK: {{\.(short|hword|2byte)}} 5
// CHECK-NOT: {{\.(short|hword|2byte|half)}} 2
// CHECK-NOT: {{\.(short|hword|2byte|half)}} 4
// CHECK: {{\.(short|hword|2byte|half)}} 5
2 changes: 2 additions & 0 deletions tests/codegen/const-vector.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
#![feature(simd_ffi)]
#![feature(arm_target_feature)]
#![feature(mips_target_feature)]
#![feature(riscv_target_feature)]
#![allow(non_camel_case_types)]

// Setting up structs that can be used as const vectors
Expand Down Expand Up @@ -51,6 +52,7 @@ extern "unadjusted" {
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
pub fn do_call() {
unsafe {
// CHECK: call void @test_i8x2(<2 x i8> <i8 32, i8 64>
Expand Down
127 changes: 127 additions & 0 deletions tests/codegen/enum/enum-aggregate-riscv64.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,127 @@
//@ compile-flags: -Copt-level=0 -Cno-prepopulate-passes
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why split this out to a separate file? Skimming the contents I don't see major differences vs the existing file. Maybe we could use revisions instead if there's a few small differences (see tests/codegen/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs for example).

Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The difference lies in the // CHECK lines. Would it be possible to separate them using revisions?

//@ min-llvm-version: 19
//@ only-64bit
//@ only-riscv64

#![crate_type = "lib"]

use std::cmp::Ordering;
use std::num::NonZero;
use std::ptr::NonNull;

#[no_mangle]
fn make_some_bool(x: bool) -> Option<bool> {
// CHECK-LABEL: i8 @make_some_bool(i1 zeroext %x)
// CHECK-NEXT: start:
// CHECK-NEXT: %[[WIDER:.+]] = zext i1 %x to i8
// CHECK-NEXT: ret i8 %[[WIDER]]
Some(x)
}

#[no_mangle]
fn make_none_bool() -> Option<bool> {
// CHECK-LABEL: i8 @make_none_bool()
// CHECK-NEXT: start:
// CHECK-NEXT: ret i8 2
None
}

#[no_mangle]
fn make_some_ordering(x: Ordering) -> Option<Ordering> {
// CHECK-LABEL: i8 @make_some_ordering(i8 signext %x)
// CHECK-NEXT: start:
// CHECK-NEXT: ret i8 %x
Some(x)
}

#[no_mangle]
fn make_some_u16(x: u16) -> Option<u16> {
// CHECK-LABEL: { i16, i16 } @make_some_u16(i16 zeroext %x)
// CHECK-NEXT: start:
// CHECK-NEXT: %0 = insertvalue { i16, i16 } { i16 1, i16 poison }, i16 %x, 1
// CHECK-NEXT: ret { i16, i16 } %0
Some(x)
}

#[no_mangle]
fn make_none_u16() -> Option<u16> {
// CHECK-LABEL: { i16, i16 } @make_none_u16()
// CHECK-NEXT: start:
// CHECK-NEXT: ret { i16, i16 } { i16 0, i16 undef }
None
}

#[no_mangle]
fn make_some_nzu32(x: NonZero<u32>) -> Option<NonZero<u32>> {
// CHECK-LABEL: i32 @make_some_nzu32(i32 signext %x)
// CHECK-NEXT: start:
// CHECK-NEXT: ret i32 %x
Some(x)
}

#[no_mangle]
fn make_ok_ptr(x: NonNull<u16>) -> Result<NonNull<u16>, usize> {
// CHECK-LABEL: { i64, ptr } @make_ok_ptr(ptr %x)
// CHECK-NEXT: start:
// CHECK-NEXT: %0 = insertvalue { i64, ptr } { i64 0, ptr poison }, ptr %x, 1
// CHECK-NEXT: ret { i64, ptr } %0
Ok(x)
}

#[no_mangle]
fn make_ok_int(x: usize) -> Result<usize, NonNull<u16>> {
// CHECK-LABEL: { i64, ptr } @make_ok_int(i64 %x)
// CHECK-NEXT: start:
// CHECK-NEXT: %[[NOPROV:.+]] = getelementptr i8, ptr null, i64 %x
// CHECK-NEXT: %[[R:.+]] = insertvalue { i64, ptr } { i64 0, ptr poison }, ptr %[[NOPROV]], 1
// CHECK-NEXT: ret { i64, ptr } %[[R]]
Ok(x)
}

#[no_mangle]
fn make_some_ref(x: &u16) -> Option<&u16> {
// CHECK-LABEL: ptr @make_some_ref(ptr align 2 %x)
// CHECK-NEXT: start:
// CHECK-NEXT: ret ptr %x
Some(x)
}

#[no_mangle]
fn make_none_ref<'a>() -> Option<&'a u16> {
// CHECK-LABEL: ptr @make_none_ref()
// CHECK-NEXT: start:
// CHECK-NEXT: ret ptr null
None
}

#[inline(never)]
fn make_err_generic<E>(e: E) -> Result<u32, E> {
// CHECK-LABEL: define{{.+}}make_err_generic
// CHECK-NEXT: start:
// CHECK-NEXT: call void @llvm.trap()
// CHECK-NEXT: ret i32 poison
Err(e)
}

#[no_mangle]
fn make_uninhabited_err_indirectly(n: Never) -> Result<u32, Never> {
// CHECK-LABEL: i32 @make_uninhabited_err_indirectly()
// CHECK-NEXT: start:
// CHECK-NEXT: call{{.+}}make_err_generic
make_err_generic(n)
}

#[no_mangle]
fn make_fully_uninhabited_result(v: u32, n: Never) -> Result<(u32, Never), (Never, u32)> {
// Actually reaching this would be UB, so we don't actually build a result.

// CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 signext %v)
// CHECK-NEXT: start:
// CHECK-NEXT: call void @llvm.trap()
// CHECK-NEXT: call void @llvm.trap()
// CHECK-NEXT: call void @llvm.trap()
// CHECK-NEXT: unreachable
Ok((v, n))
}

enum Never {}
8 changes: 4 additions & 4 deletions tests/codegen/enum/enum-aggregate.rs
Original file line number Diff line number Diff line change
Expand Up @@ -27,15 +27,15 @@ fn make_none_bool() -> Option<bool> {

#[no_mangle]
fn make_some_ordering(x: Ordering) -> Option<Ordering> {
// CHECK-LABEL: i8 @make_some_ordering(i8 %x)
// CHECK-LABEL: i8 @make_some_ordering(i8 {{.*}}%x)
// CHECK-NEXT: start:
// CHECK-NEXT: ret i8 %x
Some(x)
}

#[no_mangle]
fn make_some_u16(x: u16) -> Option<u16> {
// CHECK-LABEL: { i16, i16 } @make_some_u16(i16 %x)
// CHECK-LABEL: { i16, i16 } @make_some_u16(i16 {{.*}}%x)
// CHECK-NEXT: start:
// CHECK-NEXT: %0 = insertvalue { i16, i16 } { i16 1, i16 poison }, i16 %x, 1
// CHECK-NEXT: ret { i16, i16 } %0
Expand All @@ -52,7 +52,7 @@ fn make_none_u16() -> Option<u16> {

#[no_mangle]
fn make_some_nzu32(x: NonZero<u32>) -> Option<NonZero<u32>> {
// CHECK-LABEL: i32 @make_some_nzu32(i32 %x)
// CHECK-LABEL: i32 @make_some_nzu32(i32 {{.*}}%x)
// CHECK-NEXT: start:
// CHECK-NEXT: ret i32 %x
Some(x)
Expand Down Expand Up @@ -114,7 +114,7 @@ fn make_uninhabited_err_indirectly(n: Never) -> Result<u32, Never> {
fn make_fully_uninhabited_result(v: u32, n: Never) -> Result<(u32, Never), (Never, u32)> {
// Actually reaching this would be UB, so we don't actually build a result.

// CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 %v)
// CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 {{.*}}%v)
// CHECK-NEXT: start:
// CHECK-NEXT: call void @llvm.trap()
// CHECK-NEXT: call void @llvm.trap()
Expand Down
27 changes: 18 additions & 9 deletions tests/codegen/simd/extract-insert-dyn.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
repr_simd,
arm_target_feature,
mips_target_feature,
s390x_target_feature
s390x_target_feature,
riscv_target_feature
)]
#![no_std]
#![crate_type = "lib"]
Expand All @@ -25,97 +26,105 @@ pub struct u32x16([u32; 16]);
pub struct i8x16([i8; 16]);

// CHECK-LABEL: dyn_simd_extract
// CHECK: extractelement <16 x i8> %x, i32 %idx
// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 %idx
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn dyn_simd_extract(x: i8x16, idx: u32) -> i8 {
simd_extract_dyn(x, idx)
}

// CHECK-LABEL: literal_dyn_simd_extract
// CHECK: extractelement <16 x i8> %x, i32 7
// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn literal_dyn_simd_extract(x: i8x16) -> i8 {
simd_extract_dyn(x, 7)
}

// CHECK-LABEL: const_dyn_simd_extract
// CHECK: extractelement <16 x i8> %x, i32 7
// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn const_dyn_simd_extract(x: i8x16) -> i8 {
simd_extract_dyn(x, const { 3 + 4 })
}

// CHECK-LABEL: const_simd_extract
// CHECK: extractelement <16 x i8> %x, i32 7
// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn const_simd_extract(x: i8x16) -> i8 {
simd_extract(x, const { 3 + 4 })
}

// CHECK-LABEL: dyn_simd_insert
// CHECK: insertelement <16 x i8> %x, i8 %e, i32 %idx
// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 %idx
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn dyn_simd_insert(x: i8x16, e: i8, idx: u32) -> i8x16 {
simd_insert_dyn(x, idx, e)
}

// CHECK-LABEL: literal_dyn_simd_insert
// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7
// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn literal_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 {
simd_insert_dyn(x, 7, e)
}

// CHECK-LABEL: const_dyn_simd_insert
// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7
// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn const_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 {
simd_insert_dyn(x, const { 3 + 4 }, e)
}

// CHECK-LABEL: const_simd_insert
// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7
// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7
#[no_mangle]
#[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))]
#[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))]
#[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))]
#[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))]
#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))]
unsafe extern "C" fn const_simd_insert(x: i8x16, e: i8) -> i8x16 {
simd_insert(x, const { 3 + 4 }, e)
}
Loading
Loading