Remove weak symbols, use abort for defaults.

riscv-rt/CHANGELOG.md

@@ -62,6 +62,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   allow users get the initial address of the heap when initializing an allocator.
 - Update documentation.
 - Removed `.init.rust` section, as it is no longer required.
+- Add global `_abort` symbol, `PROVIDE(abort = _abort)`, and replace `DefaultHandler` and
+  `ExceptionHandler` with `PROVIDE(... = abort)`.
 
 ## [v0.13.0] - 2024-10-19
 

riscv-rt/link.x.in

@@ -22,18 +22,22 @@
   means that you won't see "Address (..) is out of bounds" in the disassembly produced by `objdump`.
 */
 
+/* Default abort entry point. If no abort symbol is provided, then abort maps to _abort. */
+EXTERN(_default_abort);
+PROVIDE(abort = _default_abort);
+
 /* Default trap entry point. The riscv-rt crate provides a weak alias of this function,
    which saves caller saved registers, calls _start_trap_rust, restores caller saved registers
    and then returns. Users can override this alias by defining the symbol themselves */
 EXTERN(_start_trap);
 
-/* Default exception handler. The riscv-rt crate provides a weak alias of this function,
-   which is a busy loop. Users can override this alias by defining the symbol themselves */
-EXTERN(ExceptionHandler);
+/* Default exception handler. By default, the exception handler is abort.
+   Users can override this alias by defining the symbol themselves */
+PROVIDE(ExceptionHandler = abort);
 
-/* Default interrupt handler. The riscv-rt crate provides a weak alias of this function,
-   which is a busy loop. Users can override this alias by defining the symbol themselves */
-EXTERN(DefaultHandler);
+/* Default interrupt handler. By default, the interrupt handler is abort.
+   Users can override this alias by defining the symbol themselves */
+PROVIDE(DefaultHandler = abort);
 
 /* Default interrupt trap entry point. When vectored trap mode is enabled,
    the riscv-rt crate provides an implementation of this function, which saves caller saved

riscv-rt/src/asm.rs

@@ -251,16 +251,6 @@ _setup_interrupts:",
     #[cfg(not(feature = "s-mode"))]
     "csrw mtvec, t0",
     "ret",
-    // Default implementation of `ExceptionHandler` is an infinite loop.
-    // Users can override this function by defining their own `ExceptionHandler`
-    ".weak ExceptionHandler
-ExceptionHandler:
-    j ExceptionHandler",
-    // Default implementation of `DefaultHandler` is an infinite loop.
-    // Users can override this function by defining their own `DefaultHandler`
-    ".weak DefaultHandler
-DefaultHandler:
-    j DefaultHandler",
     // Default implementation of `_pre_init_trap` is an infinite loop.
     // Users can override this function by defining their own `_pre_init_trap`
     // If the execution reaches this point, it means that there is a bug in the boot code.
@@ -278,7 +268,7 @@ riscv_rt_macros::vectored_interrupt_trap!();
 #[rustfmt::skip]
 global_asm!(
     ".section .text.abort
-.weak abort
-abort:  // make sure there is an abort symbol when linking
-    j abort"
+.global _default_abort
+_default_abort:  // make sure there is an abort symbol when linking
+    j _default_abort"
 );