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@Dirbaio Dirbaio commented Aug 21, 2022

depends on #109, #110

This is unsound on multicore systems because it only disables interrupts in the
current core. For multicore chips, a chip-specific critical section implementation
is needed instead.

Unsoundness is fixed by not returning the CriticalSection token.

This is a breaking change.

This is the riscv equivalent of rust-embedded/cortex-m#447

This shouldn't be a breaking change since Edition 2021 came out in
Rust 1.56, and MSRV is already higher than that (Rust 1.59)
This is unsound on multicore systems because it only disables interrupts in the
current core. For multicore chips, a chip-specific critical section implementation
is needed instead.

Unsoundness is fixed by not returning the `CriticalSection` token.

This is a breaking change.
@Dirbaio Dirbaio requested a review from a team as a code owner August 21, 2022 22:26
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Again, lgtm. Defer to disasm/almindor for final review.

/// # Note
/// this macro is unsound on multi-core systems
///
/// this macro requires a `critical-section` implementation to be set. For single core systems, you can
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Maybe feature-gate this macro with critical-section-single-core?

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The macro can still be used if critical-section-single-core is not enabled, if the user supplies a c-s implementation from somewhere else (such as a chip-specific impl for a multicore chip, from its HAL crate).

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Dirbaio commented Aug 22, 2022

Folded into #110

@Dirbaio Dirbaio closed this Aug 22, 2022
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3 participants