Brett/dev/no ints #4
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* add support for the ariane soc based genesys2 board * bugfix :: correct mtime register offsets * bugfix :: correct the clock-frequency for uart0 Co-authored-by: akif <[email protected]>
* add support for the ariane soc based genesys2 board includes a super simple test to verify printk, and a basic kernel launch of our "app". * revert sample app to default * bugfix :: correct mtime register offsets * bugfix :: correct the clock-frequency for uart0 * Modified ariane.dtsi file to add the xlnx_gpio0 support. This required a small change in yaml binding file to make a property optional. Also, cleaned the pinmux file so that it can be filled appropriately. modified: boards/riscv/genesys2/genesys2.dts modified: boards/riscv/genesys2/pinmux.c modified: dts/bindings/gpio/xlnx,xlnx,xps-gpio-1.00.a.yaml modified: dts/riscv/rv64_ariane.dtsi Co-authored-by: akif <[email protected]> Co-authored-by: Akif Saglam <[email protected]>
* Modified ariane.dtsi file to add the xlnx_gpio0 support. This required a small change in yaml binding file to make a property optional. Also, cleaned the pinmux file so that it can be filled appropriately. * bug fix :: Correct gpio reg addressing * bug fix:: Correct SYS_CLOCK_HW_CYCLES_PER_SEC
systems with CLINT & PLIC setups. Can build with ints enabled, chars come out but isr is never called. Get rid of various hacks
sabhiram
requested changes
Jan 22, 2021
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config BOARD_GENESYS2 | ||
| bool "Recogni Genesys2 FPGA target" |
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Should this have the SiFive copyright?
| @@ -0,0 +1,17 @@ | |||
| # Copyright (c) 2019 SiFive Inc. | |||
| @@ -0,0 +1,45 @@ | |||
| .. _hifive1_revb: | |||
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This should be updated to the genesys info.
| mmu-type = "riscv,sv39"; | ||
| tlb-split; | ||
| // HLIC - hart local interrupt controller | ||
| CPU0_intc: interrupt-controller { |
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I prefer calling this the hlic - ill update this stuff after we merge.
| while (1) { | ||
| gpio_pin_set(dev, PIN, (int)led_is_on); | ||
| led_is_on = !led_is_on; | ||
| printk("Going to sleep..\n"); |
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We should not be editing the sample apps at all. This will never get accepted upsteream.
| void main(void) | ||
| { | ||
| printk("Hello World! %s\n", CONFIG_BOARD); | ||
| printk("Hello from zephyr! %s %s %s\n", CONFIG_BOARD, __DATE__, __TIME__); |
berendo
pushed a commit
that referenced
this pull request
Apr 9, 2021
This makes the gatt metrics also available for gatt write-without-rsp-cb so it now prints the rate of each write: uart:~$ gatt write-without-response-cb 1e ff 10 10 Write #1: 16 bytes (0 bps) Write #2: 32 bytes (3445948416 bps) Write #3: 48 bytes (2596929536 bps) Write #4: 64 bytes (6400 bps) Write #5: 80 bytes (8533 bps) Write #6: 96 bytes (10666 bps) Write #7: 112 bytes (8533 bps) Write #8: 128 bytes (9955 bps) Write #9: 144 bytes (11377 bps) Write #10: 160 bytes (7680 bps) Write #11: 176 bytes (8533 bps) Write #12: 192 bytes (9386 bps) Write Complete (err 0) Write #13: 208 bytes (8533 bps) Write #14: 224 bytes (9244 bps) Write #15: 240 bytes (9955 bps) Write #16: 256 bytes (8000 bps) Signed-off-by: Luiz Augusto von Dentz <[email protected]>
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feature: Clone the ns15560 uart driver as digilent_15560 so we can modify it it for PLIC/CLINT systems without disturbing legacy users.