Strongly typed RISC-V Page Table & Hypervisor Extension #3
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gjz010
changed the title
| self.0.try_into().unwrap() | ||
| } | ||
| fn page_number(&self) -> usize { | ||
| self.0.get_bits(12..64).try_into().unwrap() |
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| assert!(p3_index.get_bits(12..) == 0, "p3_index exceeding 11 bits"); | ||
| assert!(p2_index.get_bits(10..) == 0, "p2_index exceeding 9 bits"); | ||
| assert!(p1_index.get_bits(10..) == 0, "p1_index exceeding 9 bits"); |
| let mut addr = | ||
| (p3_index << 12 << 9 << 9) | (p2_index << 12 << 9) | (p1_index << 12) | offset; | ||
| if addr.get_bit(38) { | ||
| addr.set_bits(39..64, 0xFFFF); |
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should be (1 << (64 - 39)) - 1?
| impl AddressX64 for VirtAddrSv39 { | ||
| fn new_u64(addr: u64) -> Self { | ||
| if addr.get_bit(38) { | ||
| assert!(addr.get_bits(39..64) == 0xFFFF, "va 39..64 is not sext"); |
There was a problem hiding this comment.
should be (1 << (64 - 39)) - 1?
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| assert!(p4_index.get_bits(10..) == 0, "p4_index exceeding 9 bits"); | ||
| assert!(p3_index.get_bits(10..) == 0, "p3_index exceeding 9 bits"); | ||
| assert!(p2_index.get_bits(10..) == 0, "p2_index exceeding 9 bits"); | ||
| assert!(p1_index.get_bits(10..) == 0, "p1_index exceeding 9 bits"); |
| self.0.try_into().unwrap() | ||
| } | ||
| fn page_number(&self) -> usize { | ||
| self.0.get_bits(12..64).try_into().unwrap() |
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