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Ziyue Zhang and others added 5 commits October 30, 2025 17:50
…form

This update enables PCIe5 support by adding necessary sideband signals
(PERST#, WAKE#, CLKREQ#) and required regulators to the PCIe3 controller
and PHY device tree nodes.

These changes ensure correct link initialization and power sequencing for
devices connected via PCIe5.

Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Ziyue Zhang <[email protected]>
Reviewed-by: Krishna Chaitanya Chundru <[email protected]>
…VK board

Specify the vddpe-3v3-supply regulator for PCIe5 using &vreg_wwan to
ensure proper power configuration.

Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Ziyue Zhang <[email protected]>
Reviewed-by: Krishna Chaitanya Chundru <[email protected]>
…form

This update enables PCIe3 support by adding necessary sideband signals
(PERST#, WAKE#, CLKREQ#) and required regulators to the PCIe3 controller
and PHY device tree nodes.

These changes ensure correct link initialization and power sequencing for
devices connected via PCIe3.

Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Ziyue Zhang <[email protected]>
…oard

HAMOA-IOT-EVK board includes a PCIe3 controller and x8 slot that require
proper power rail and control signal configuration. This update adds
`vddpe-3v3-supply` and `regulator-pcie-12v` to provide 3.3V to the PHY
and 12V to the slot for external devices.

It also introduces PM GPIOs to manage power enable and reset signals,
ensuring stable power sequencing and reliable PCIe3 operation.

Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Ziyue Zhang <[email protected]>
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