ROCm Sparse Marlin Kernels #1206 #1834
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ROCm build infrastructure
[ROCm] Enable Tiled layout extension and minor changes to setup
Fixes builds for non-rocm.
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/1834
Note: Links to docs will display an error until the docs builds have been completed. ❌ 1 New Failure, 1 Pending, 1 Unrelated FailureAs of commit 15e29f1 with merge base 883dc65 ( NEW FAILURE - The following job has failed:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This is a dupe of #1206, just needed to fix some setup.py stuff and didn't have write access to the fork |
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* enable build for rocm for fp6_llm * enable tiled layout extension * fix build error related to option * require rocm 6.2 * enable tensor tiled layout extension with successful compilation * clean-up * fix potential memory access issue * fix __nv_bfloat162 init * add comment for MI300x isa * fix build for non-rocm * add sparse_marlin kernel to the build * drop .h from conversion * cp_asyc4_pred_zfill() AMD implementation * implement matching mem utility with amd GCN isa * implement mma util with amd gcn isa * enable rocm path * update copy from global to lds * implement cvta_to_shared() * consolidate code with cvta_to_shared() * lint * add GPU arch check for MI300x * revert change in tensor_core_tile_layout.cu * lint refactor for better readibility * fix setup --------- Co-authored-by: lcskrishna <[email protected]> Co-authored-by: Peter Yeh <[email protected]> Co-authored-by: Peter Y. Yeh <[email protected]>
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Built on top pf #1201. This pull request introduces support for ROCm (Radeon Open Compute) for sparse marling kernel in addition to CUDA, enabling the code to run on AMD GPUs.
The main changes involve conditional compilation to handle differences between CUDA and ROCm, as well as adding ROCm-specific intrinsics for MI300x.
co-author : @lcskrishna
Key changes include:
ROCm Support in
setup.py:Conditional Compilation in CUDA Source Files:
ROCm-specific Implementations:
Next: