Fixes for cAVS 2.5 / Tigerlake #9
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RAM window layout differs between cAVS versions. Fix an apparent copy-paste definition block to match cAVS 2.5. Signed-off-by: Guennadi Liakhovetski <[email protected]>
Tigerlake H has less RAM and fewer cores. Both should be supported, selectable at the board level. For now use the H configuration as more readily available for testing. Signed-off-by: Guennadi Liakhovetski <[email protected]>
shim.h on cAVS 2.5 contains register definitions, copy-pasted from other architectures. Fix them to correct values. Signed-off-by: Guennadi Liakhovetski <[email protected]>
CONFIG_BOOTLOADER_MCUBOOT is never defined in cAVS builds, code, built only when that option is enabled, contains invalid expressions. Fix them. Signed-off-by: Guennadi Liakhovetski <[email protected]>
LSPGISTS and LSPGCTL are located in a different shim register range, they cannot be accessed, using the usual SHIM_BASE offset. Signed-off-by: Guennadi Liakhovetski <[email protected]>
nashif
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Jan 4, 2021
nashif
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Mar 18, 2024
D9/SCK pin is #9 pin, not #0. Signed-off-by: TOKITA Hiroshi <[email protected]>
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I'll add a couple more commits to this PR tomorrow to also fix similar issues in cAVS 1.8 and 2.0