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[SelectionDAG] Use unaligned store to legalize EXTRACT_VECTOR_ELT type when Stack is non-realignable #98176

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Merged
merged 1 commit into from
Jul 29, 2024
Merged

[SelectionDAG] Use unaligned store to legalize EXTRACT_VECTOR_ELT type when Stack is non-realignable #98176

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5 changes: 5 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2481,6 +2481,11 @@ Align SelectionDAG::getReducedAlign(EVT VT, bool UseABI) {
Align RedAlign2 = UseABI ? DL.getABITypeAlign(Ty) : DL.getPrefTypeAlign(Ty);
if (RedAlign2 < RedAlign)
RedAlign = RedAlign2;

if (!getMachineFunction().getFrameInfo().isStackRealignable())
// If the stack is not realignable, the alignment should be limited to the
// StackAlignment
RedAlign = std::min(RedAlign, StackAlign);
}

return RedAlign;
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
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Expand Up @@ -17,4 +17,22 @@ entry:
ret i32 %b
}

define i32 @foo2(i32 %arg1) #1 {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $31, %edi
; CHECK-NEXT: movzwl -72(%rsp,%rdi,2), %eax
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
%a = extractelement <32 x i16> zeroinitializer, i32 %arg1
%b = zext i16 %a to i32
ret i32 %b
}

attributes #0 = { "no-realign-stack" "target-cpu"="skylake-avx512" }
attributes #1 = { "no-realign-stack" "target-cpu"="skylake" }