Skip to content
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions llvm/include/llvm/IR/IntrinsicsRISCV.td
Original file line number Diff line number Diff line change
Expand Up @@ -144,14 +144,14 @@ class RISCVVIntrinsic {

let TargetPrefix = "riscv" in {
// We use anyint here but we only support XLen.
def int_riscv_vsetvli : Intrinsic<[llvm_anyint_ty],
def int_riscv_vsetvli : DefaultAttrsIntrinsic<[llvm_anyint_ty],
/* AVL */ [LLVMMatchType<0>,
/* VSEW */ LLVMMatchType<0>,
/* VLMUL */ LLVMMatchType<0>],
[IntrNoMem,
ImmArg<ArgIndex<1>>,
ImmArg<ArgIndex<2>>]>;
def int_riscv_vsetvlimax : Intrinsic<[llvm_anyint_ty],
def int_riscv_vsetvlimax : DefaultAttrsIntrinsic<[llvm_anyint_ty],
/* VSEW */ [LLVMMatchType<0>,
/* VLMUL */ LLVMMatchType<0>],
[IntrNoMem,
Expand Down Expand Up @@ -669,7 +669,7 @@ let TargetPrefix = "riscv" in {
// The destination vector type is the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vxrm, vl)
class RISCVSaturatingBinaryAAXUnMaskedRoundingMode
: Intrinsic<[llvm_anyvector_ty],
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
llvm_anyint_ty, LLVMMatchType<2>],
[ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
Expand All @@ -692,7 +692,7 @@ let TargetPrefix = "riscv" in {
// The destination vector type is the same as first source vector.
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl, policy)
class RISCVSaturatingBinaryAAXMaskedRoundingMode
: Intrinsic<[llvm_anyvector_ty],
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>, LLVMMatchType<2>],
Expand Down