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@topperc topperc commented Dec 2, 2023

The computation we use for computing the size already returns 0 when all registers are allocated. We don't need an if to set it to 0.

Use the size being 0 to check for whether we need to spill registers or not.

I have another change I want to make to this code, but this change seemed to stand on its own. I left the curly braces since I need them for the other change.

…ase. NFC

The computation we use for computing the size already returns 0
when all registers are allocated. We don't need an if to set it to 0.

Use the size being 0 to check for whether we need to spill registers
or not.

I have another change I want to make to this code, but this change
seemed to stand on its own. I left the curly braces since I need
them for the other change.
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llvmbot commented Dec 2, 2023

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

The computation we use for computing the size already returns 0 when all registers are allocated. We don't need an if to set it to 0.

Use the size being 0 to check for whether we need to spill registers or not.

I have another change I want to make to this code, but this change seemed to stand on its own. I left the curly braces since I need them for the other change.


Full diff: https://github.com/llvm/llvm-project/pull/74209.diff

2 Files Affected:

  • (modified) llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp (+4-4)
  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-4)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
index bd602635dd5f7..9e96fba069c4e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
@@ -441,14 +441,14 @@ void RISCVCallLowering::saveVarArgRegisters(
   // Offset of the first variable argument from stack pointer, and size of
   // the vararg save area. For now, the varargs save area is either zero or
   // large enough to hold a0-a7.
-  int VaArgOffset, VarArgsSaveSize;
+  int VaArgOffset;
+  int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
+
   // If all registers are allocated, then all varargs must be passed on the
   // stack and we don't need to save any argregs.
-  if (ArgRegs.size() == Idx) {
+  if (VarArgsSaveSize == 0) {
     VaArgOffset = Assigner.StackSize;
-    VarArgsSaveSize = 0;
   } else {
-    VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
     VaArgOffset = -VarArgsSaveSize;
   }
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 241bc96766f29..cf1b11c14b6d0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17694,15 +17694,14 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
     // Offset of the first variable argument from stack pointer, and size of
     // the vararg save area. For now, the varargs save area is either zero or
     // large enough to hold a0-a7.
-    int VaArgOffset, VarArgsSaveSize;
+    int VaArgOffset;
+    int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
 
     // If all registers are allocated, then all varargs must be passed on the
     // stack and we don't need to save any argregs.
-    if (ArgRegs.size() == Idx) {
+    if (VarArgsSaveSize == 0) {
       VaArgOffset = CCInfo.getStackSize();
-      VarArgsSaveSize = 0;
     } else {
-      VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
       VaArgOffset = -VarArgsSaveSize;
     }
 

@topperc topperc changed the title [RISCV] Compute VarArgsSaveSize even for the all register allocated case. NFC [RISCV] Simplify computation of VarArgsSaveSize. NFC Dec 3, 2023
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LGTM.

@topperc topperc merged commit 26fc26c into llvm:main Dec 4, 2023
@topperc topperc deleted the pr/varargssize branch December 4, 2023 04:35
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3 participants