Skip to content

[SelectionDAG] [NFC] Add pre-commit test for PR66701. #66796

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 20, 2023
Merged

[SelectionDAG] [NFC] Add pre-commit test for PR66701. #66796

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
24 changes: 24 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fma.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -154,3 +154,27 @@ define float @fold_fmul_distributive(float %x, float %y) {
%fmul = fmul contract float %fadd, %x
ret float %fmul
}

; test to make sure contract is not dropped such that we can generate fma from following mul/add
define amdgpu_kernel void @vec_mul_scalar_add_fma(<2 x float> %a, <2 x float> %b, float %c1, ptr addrspace(1) %inptr) {
; GFX906-LABEL: vec_mul_scalar_add_fma:
; GFX906: ; %bb.0:
; GFX906-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
; GFX906-NEXT: s_load_dword s5, s[0:1], 0x34
; GFX906-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x3c
; GFX906-NEXT: v_mov_b32_e32 v0, 0
; GFX906-NEXT: v_mov_b32_e32 v1, s6
; GFX906-NEXT: v_mul_f32_e32 v1, s4, v1
; GFX906-NEXT: s_waitcnt lgkmcnt(0)
; GFX906-NEXT: v_add_f32_e32 v1, s5, v1
; GFX906-NEXT: global_store_dword v0, v1, s[2:3] offset:4
; GFX906-NEXT: s_endpgm
%gep = getelementptr float, ptr addrspace(1) %inptr, i32 1
%c = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> zeroinitializer
%mul = fmul contract <2 x float> %c, %b
%elv = extractelement <2 x float> %mul, i64 0
%add = fadd contract float %elv, %c1
store float %add, ptr addrspace(1) %gep, align 4
ret void
}