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[GlobalISel] Port computeNumSignBits for G_MUL #167311

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[GlobalISel] Port computeNumSignBits for G_MUL #167311

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ad0db4f
Port computeNumSignBits for G_MUL
AnushaK6 Nov 10, 2025
333a8ae
Correct test checks that use mul
AnushaK6 Nov 10, 2025
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36 changes: 36 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/ConstantRange.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/FMF.h"
#include "llvm/MC/TargetRegistry.h"
Expand Down Expand Up @@ -2084,6 +2085,41 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits) - 1;
break;
}
case TargetOpcode::G_MUL: {
Register Src1 = MI.getOperand(1).getReg();
Register Src2 = MI.getOperand(2).getReg();

KnownBits Known1 = getKnownBits(Src1, DemandedElts, Depth + 1);
KnownBits Known2 = getKnownBits(Src2, DemandedElts, Depth + 1);

if (Known1.isZero() || Known2.isZero())
return TyBits;
Comment on lines +2092 to +2096
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@arsenm arsenm Nov 11, 2025

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I don't think you need to call getKnownBits at all here. The DAG version doesn't. 0 also shouldn't need a special case


auto C1 = getIConstantVRegValWithLookThrough(Src1, MRI);
auto C2 = getIConstantVRegValWithLookThrough(Src2, MRI);

if (C1 && C2) {
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@arsenm arsenm Nov 11, 2025

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Don't need to worry about trying to handle constants specially

APInt Val1 = C1->Value;
APInt Val2 = C2->Value;
APInt Product = Val1 * Val2;
return Product.getNumSignBits();
}
unsigned Src1NumSignBits =
computeNumSignBits(Src1, DemandedElts, Depth + 1);
if (Src1NumSignBits == 1) {
return 1;
}
unsigned Src2NumSignBits =
computeNumSignBits(Src2, DemandedElts, Depth + 1);
if (Src2NumSignBits == 1) {
return 1;
}
Comment on lines +2112 to +2116
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@arsenm arsenm Nov 11, 2025

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Compute src2 before src1, as it's canonically cheaper


unsigned OutValidBits =
(TyBits - Src1NumSignBits + 1) + (TyBits - Src2NumSignBits + 1);
FirstAnswer = OutValidBits > TyBits ? 1 : TyBits - OutValidBits + 1;
break;
}
case TargetOpcode::G_FCMP:
case TargetOpcode::G_ICMP: {
bool IsFP = Opcode == TargetOpcode::G_FCMP;
Expand Down
79 changes: 79 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/knownbits-mul.mir
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@@ -0,0 +1,79 @@
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s

---
name: ConstPositives
body: |
bb.1:
; CHECK-LABEL: name: @ConstPositives
; CHECK-NEXT: %0:_ KnownBits:00000011 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00000101 SignBits:5
; CHECK-NEXT: %2:_ KnownBits:00001111 SignBits:4
%0:_(s8) = G_CONSTANT i8 3
%1:_(s8) = G_CONSTANT i8 5
%2:_(s8) = G_MUL %0, %1
...
---
name: ConstZero
body: |
bb.1:
; CHECK-LABEL: name: @ConstZero
; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8
; CHECK-NEXT: %1:_ KnownBits:00000001 SignBits:7
; CHECK-NEXT: %2:_ KnownBits:00000000 SignBits:8
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_MUL %0, %1
...
---
name: ConstNegatives
body: |
bb.1:
; CHECK-LABEL: name: @ConstNegatives
; CHECK-NEXT: %0:_ KnownBits:11111110 SignBits:7
; CHECK-NEXT: %1:_ KnownBits:11111100 SignBits:6
; CHECK-NEXT: %2:_ KnownBits:00001000 SignBits:4
%0:_(s8) = G_CONSTANT i8 -2
%1:_(s8) = G_CONSTANT i8 -4
%2:_(s8) = G_MUL %0, %1
...
---
name: MixedSigns
body: |
bb.1:
; CHECK-LABEL: name: @MixedSigns
; CHECK-NEXT: %0:_ KnownBits:11111100 SignBits:6
; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
; CHECK-NEXT: %2:_ KnownBits:11110100 SignBits:4
%0:_(s8) = G_CONSTANT i8 -4
%1:_(s8) = G_CONSTANT i8 3
%2:_(s8) = G_MUL %0, %1
...
---
name: UnknownVar
body: |
bb.1:
; CHECK-LABEL: name: @UnknownVar
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
; CHECK-NEXT: %2:_ KnownBits:???????0 SignBits:1
%0:_(s8) = COPY $b0
%1:_(s8) = G_CONSTANT i8 2
%2:_(s8) = G_MUL %0, %1
...
---
name: VectorMul
body: |
bb.1:
; CHECK-LABEL: name: @VectorMul
; CHECK-NEXT: %0:_ KnownBits:0000000000000001 SignBits:15
; CHECK-NEXT: %1:_ KnownBits:0000000000000010 SignBits:14
; CHECK-NEXT: %2:_ KnownBits:00000000000000?? SignBits:14
; CHECK-NEXT: %3:_ KnownBits:00000000000000?? SignBits:14
; CHECK-NEXT: %4:_ KnownBits:000000000000???? SignBits:12
%0:_(s16) = G_CONSTANT i16 1
%1:_(s16) = G_CONSTANT i16 2
%2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
%3:_(<4 x s16>) = G_BUILD_VECTOR %1, %0, %0, %1
%4:_(<4 x s16>) = G_MUL %2, %3
...
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/AArch64/combine-sdiv.ll
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Expand Up @@ -1510,7 +1510,6 @@ define i5 @combine_i5_sdiv_const7(i5 %x) {
; CHECK-GI-NEXT: sbfx w9, w0, #0, #5
; CHECK-GI-NEXT: sbfx w8, w8, #0, #5
; CHECK-GI-NEXT: mul w8, w9, w8
; CHECK-GI-NEXT: sbfx w8, w8, #0, #10
; CHECK-GI-NEXT: add w8, w0, w8, asr #5
; CHECK-GI-NEXT: sbfx w8, w8, #0, #5
; CHECK-GI-NEXT: asr w8, w8, #2
Expand Down Expand Up @@ -1560,7 +1559,6 @@ define i8 @combine_i8_sdiv_const7(i8 %x) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #-109 // =0xffffff93
; CHECK-GI-NEXT: mul w8, w8, w9
; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: add w8, w0, w8, asr #8
; CHECK-GI-NEXT: sbfx w8, w8, #2, #6
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
Expand All @@ -1585,7 +1583,7 @@ define i8 @combine_i8_sdiv_const100(i8 %x) {
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: mov w9, #41 // =0x29
; CHECK-GI-NEXT: mul w8, w8, w9
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
; CHECK-GI-NEXT: asr w8, w8, #8
; CHECK-GI-NEXT: asr w8, w8, #4
; CHECK-GI-NEXT: ubfx w9, w8, #7, #1
; CHECK-GI-NEXT: add w0, w8, w9
Expand Down
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