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[X86] narrowBitOpRMW/combineTruncate - don't retain pointer info for unknown offset load/stores #166752

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Merged
merged 1 commit into from
Nov 6, 2025
Merged

[X86] narrowBitOpRMW/combineTruncate - don't retain pointer info for unknown offset load/stores #166752

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6 changes: 4 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -53442,7 +53442,8 @@ static SDValue narrowBitOpRMW(StoreSDNode *St, const SDLoc &DL,
}

SDValue NewStore =
DAG.getStore(St->getChain(), DL, Res, NewPtr, St->getPointerInfo(),
DAG.getStore(St->getChain(), DL, Res, NewPtr,
MachinePointerInfo(St->getPointerInfo().getAddrSpace()),
Align(), St->getMemOperand()->getFlags());

// If there are other uses of StoredVal, replace with a new load of the
Expand Down Expand Up @@ -54639,7 +54640,8 @@ static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
SDValue NewPtr = DAG.getMemBasePlusOffset(
Ld->getBasePtr(), PtrByteOfs, DL, SDNodeFlags::NoUnsignedWrap);
SDValue NewLoad =
DAG.getLoad(VT, DL, Ld->getChain(), NewPtr, Ld->getPointerInfo(),
DAG.getLoad(VT, DL, Ld->getChain(), NewPtr,
MachinePointerInfo(Ld->getPointerInfo().getAddrSpace()),
Align(), Ld->getMemOperand()->getFlags());
DAG.makeEquivalentMemoryOrdering(Ld, NewLoad);
return NewLoad;
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr166744.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=haswell | FileCheck %s --check-prefixes=NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=NOPOSTRA

; FIXME: Ensure reloads are after narrowed i512 -> i32 store
; Ensure reloads are after narrowed i512 -> i32 store
define i1 @PR166744(ptr %v, i64 %idx, i1 zeroext %b) {
; POSTRA-LABEL: PR166744:
; POSTRA: # %bb.0:
Expand All @@ -12,15 +12,15 @@ define i1 @PR166744(ptr %v, i64 %idx, i1 zeroext %b) {
; POSTRA-NEXT: bextrl %eax, %esi, %eax
; POSTRA-NEXT: movl (%rdi,%rax,4), %ecx
; POSTRA-NEXT: btrl %esi, %ecx
; POSTRA-NEXT: movq 8(%rdi), %rsi
; POSTRA-NEXT: orq 40(%rdi), %rsi
; POSTRA-NEXT: orl %ecx, %edx
; POSTRA-NEXT: movl %edx, (%rdi,%rax,4)
; POSTRA-NEXT: movq 16(%rdi), %rax
; POSTRA-NEXT: movq (%rdi), %rcx
; POSTRA-NEXT: movq 24(%rdi), %rdx
; POSTRA-NEXT: movq 8(%rdi), %rsi
; POSTRA-NEXT: orq 56(%rdi), %rdx
; POSTRA-NEXT: orq 40(%rdi), %rsi
; POSTRA-NEXT: orq 48(%rdi), %rax
; POSTRA-NEXT: movq (%rdi), %rcx
; POSTRA-NEXT: orq 32(%rdi), %rcx
; POSTRA-NEXT: orq %rdx, %rsi
; POSTRA-NEXT: orq %rax, %rcx
Expand Down
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