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[InstCombine] Enable FoldOpIntoSelect and foldOpIntoPhi when the Op's other parameter is non-const #166102

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Merged
merged 4 commits into from
Nov 5, 2025
Merged

[InstCombine] Enable FoldOpIntoSelect and foldOpIntoPhi when the Op's other parameter is non-const #166102

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e9a5d95
Enable FoldOpIntoSelect when the Op's other parameter is non-const
spaits Nov 2, 2025
fa3c083
Add test cases coming from #163108
spaits Nov 4, 2025
911b97e
Add test cases coming from #137161
spaits Nov 4, 2025
306dd28
Port test from #138373
spaits Nov 4, 2025
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6 changes: 3 additions & 3 deletions llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
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Expand Up @@ -2261,11 +2261,11 @@ Instruction *InstCombinerImpl::foldBinopWithPhiOperands(BinaryOperator &BO) {
}

Instruction *InstCombinerImpl::foldBinOpIntoSelectOrPhi(BinaryOperator &I) {
if (!isa<Constant>(I.getOperand(1)))
return nullptr;
bool IsOtherParamConst = isa<Constant>(I.getOperand(1));

if (auto *Sel = dyn_cast<SelectInst>(I.getOperand(0))) {
if (Instruction *NewSel = FoldOpIntoSelect(I, Sel))
if (Instruction *NewSel =
FoldOpIntoSelect(I, Sel, false, !IsOtherParamConst))
return NewSel;
} else if (auto *PN = dyn_cast<PHINode>(I.getOperand(0))) {
if (Instruction *NewPhi = foldOpIntoPhi(I, PN))
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/Transforms/InstCombine/binop-phi-operands.ll
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Expand Up @@ -653,12 +653,11 @@ define i8 @mul_const_incoming0_speculatable(i1 %b, i8 %x, i8 %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[B:%.*]], label [[IF:%.*]], label [[THEN:%.*]]
; CHECK: if:
; CHECK-NEXT: [[TMP0:%.*]] = mul i8 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br label [[THEN]]
; CHECK: then:
; CHECK-NEXT: [[P0:%.*]] = phi i8 [ 42, [[ENTRY:%.*]] ], [ [[X:%.*]], [[IF]] ]
; CHECK-NEXT: [[P1:%.*]] = phi i8 [ 17, [[ENTRY]] ], [ [[Y:%.*]], [[IF]] ]
; CHECK-NEXT: [[R:%.*]] = phi i8 [ -54, [[ENTRY:%.*]] ], [ [[TMP0]], [[IF]] ]
; CHECK-NEXT: call void @sideeffect()
; CHECK-NEXT: [[R:%.*]] = mul i8 [[P0]], [[P1]]
; CHECK-NEXT: ret i8 [[R]]
;
entry:
Expand Down
187 changes: 186 additions & 1 deletion llvm/test/Transforms/InstCombine/binop-select.ll
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Expand Up @@ -335,7 +335,7 @@ define i32 @sub_sel_op1_use(i1 %b) {

define float @fadd_sel_op0(i1 %b, float %x) {
; CHECK-LABEL: @fadd_sel_op0(
; CHECK-NEXT: [[R:%.*]] = select nnan i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
; CHECK-NEXT: ret float [[R]]
;
%s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000
Expand Down Expand Up @@ -403,3 +403,188 @@ define i32 @ashr_sel_op1_use(i1 %b) {
%r = ashr i32 -2, %s
ret i32 %r
}

define i8 @commonArgWithOr0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr0(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithOr1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr1(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 23
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithOr2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithOr2(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 42
; CHECK-NEXT: [[V2:%.*]] = or i8 [[V1]], [[V0]]
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 42
%v2 = or i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithAnd0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd0(
; CHECK-NEXT: ret i8 16
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithAnd1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd1(
; CHECK-NEXT: ret i8 16
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 8, i8 1
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithAnd2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd2(
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithAnd3(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAnd3(
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 42
%v2 = and i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithXor0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor0(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 0, i8 8
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithXor1(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor1(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 9, i8 1
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
; CHECK-NEXT: ret i8 [[V2]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 9, i8 1
%v2 = xor i8 %v1, %v0
ret i8 %v2
}

define i8 @commonArgWithXor2(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor2(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 1, i8 7
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 1, i8 7
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithXor3(i1 %arg0) {
; CHECK-LABEL: @commonArgWithXor3(
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 45
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 45
%v2 = xor i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i8 @commonArgWithAdd0(i1 %arg0) {
; CHECK-LABEL: @commonArgWithAdd0(
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 22, i8 61
; CHECK-NEXT: ret i8 [[V3]]
;
%v0 = zext i1 %arg0 to i8
%v1 = select i1 %arg0, i8 21, i8 45
%v2 = add i8 %v1, %v0
%v3 = or i8 %v2, 16
ret i8 %v3
}

define i32 @OrSelectIcmpZero(i32 %a, i32 %b) {
; CHECK-LABEL: @OrSelectIcmpZero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 [[A]]
; CHECK-NEXT: ret i32 [[OR]]
;
%cmp = icmp eq i32 %a, 0
%sel = select i1 %cmp, i32 %b, i32 0
%or = or i32 %sel, %a
ret i32 %or
}

define i32 @OrSelectIcmpNonZero(i32 %a, i32 %b) {
; CHECK-LABEL: @OrSelectIcmpNonZero(
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 42
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL]], [[A]]
; CHECK-NEXT: ret i32 [[OR]]
;
%cmp = icmp eq i32 %a, 0
%sel = select i1 %cmp, i32 %b, i32 42
%or = or i32 %sel, %a
ret i32 %or
}
10 changes: 4 additions & 6 deletions llvm/test/Transforms/InstCombine/dont-distribute-phi.ll
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Expand Up @@ -7,7 +7,7 @@
define zeroext i1 @foo(i32 %arg) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ARG:%.*]], 37
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
; CHECK-NEXT: br i1 [[CMP1]], label [[BB_ELSE:%.*]], label [[BB_THEN:%.*]]
; CHECK: bb_then:
; CHECK-NEXT: call void @bar()
Expand All @@ -16,8 +16,7 @@ define zeroext i1 @foo(i32 %arg) {
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[ARG]], 17
; CHECK-NEXT: br label [[BB_EXIT]]
; CHECK: bb_exit:
; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ]
; CHECK-NEXT: [[AND1:%.*]] = and i1 [[PHI1]], [[CMP1]]
; CHECK-NEXT: [[AND1:%.*]] = phi i1 [ [[CMP2]], [[BB_THEN]] ], [ false, [[BB_ELSE]] ]
; CHECK-NEXT: ret i1 [[AND1]]
;

Expand All @@ -43,7 +42,7 @@ bb_exit:
define zeroext i1 @foo_logical(i32 %arg) {
; CHECK-LABEL: @foo_logical(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ARG:%.*]], 37
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
; CHECK-NEXT: br i1 [[CMP1]], label [[BB_ELSE:%.*]], label [[BB_THEN:%.*]]
; CHECK: bb_then:
; CHECK-NEXT: call void @bar()
Expand All @@ -52,8 +51,7 @@ define zeroext i1 @foo_logical(i32 %arg) {
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[ARG]], 17
; CHECK-NEXT: br label [[BB_EXIT]]
; CHECK: bb_exit:
; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ]
; CHECK-NEXT: [[AND1:%.*]] = and i1 [[PHI1]], [[CMP1]]
; CHECK-NEXT: [[AND1:%.*]] = phi i1 [ [[CMP2]], [[BB_THEN]] ], [ false, [[BB_ELSE]] ]
; CHECK-NEXT: ret i1 [[AND1]]
;

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/fmul.ll
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Expand Up @@ -1222,7 +1222,7 @@ define <2 x double> @negate_if_true_wrong_constant(<2 x double> %px, i1 %cond) {
; X *fast (C ? 1.0 : 0.0) -> C ? X : 0.0
define float @fmul_select(float %x, i1 %c) {
; CHECK-LABEL: @fmul_select(
; CHECK-NEXT: [[MUL:%.*]] = select fast i1 [[C:%.*]], float [[X:%.*]], float 0.000000e+00
; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], float [[X:%.*]], float 0.000000e+00
; CHECK-NEXT: ret float [[MUL]]
;
%sel = select i1 %c, float 1.0, float 0.0
Expand All @@ -1233,7 +1233,7 @@ define float @fmul_select(float %x, i1 %c) {
; X *fast (C ? 1.0 : 0.0) -> C ? X : 0.0
define <2 x float> @fmul_select_vec(<2 x float> %x, i1 %c) {
; CHECK-LABEL: @fmul_select_vec(
; CHECK-NEXT: [[MUL:%.*]] = select fast i1 [[C:%.*]], <2 x float> [[X:%.*]], <2 x float> zeroinitializer
; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], <2 x float> [[X:%.*]], <2 x float> zeroinitializer
; CHECK-NEXT: ret <2 x float> [[MUL]]
;
%sel = select i1 %c, <2 x float> <float 1.0, float 1.0>, <2 x float> zeroinitializer
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/free-inversion.ll
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Expand Up @@ -563,10 +563,10 @@ define i1 @test_inv_free(i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
; CHECK: b2:
; CHECK-NEXT: br label [[EXIT]]
; CHECK: b3:
; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[C3:%.*]], [[C4:%.*]]
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: [[VAL_NOT:%.*]] = phi i1 [ false, [[B1]] ], [ true, [[B2]] ], [ [[C3:%.*]], [[B3]] ]
; CHECK-NEXT: [[COND_NOT:%.*]] = and i1 [[VAL_NOT]], [[C4:%.*]]
; CHECK-NEXT: [[COND_NOT:%.*]] = phi i1 [ false, [[B1]] ], [ [[C4]], [[B2]] ], [ [[TMP0]], [[B3]] ]
; CHECK-NEXT: br i1 [[COND_NOT]], label [[B5:%.*]], label [[B4:%.*]]
; CHECK: b4:
; CHECK-NEXT: ret i1 true
Expand Down
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