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[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb #165035

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Merged
merged 2 commits into from
Oct 31, 2025
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[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb #165035

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a6b1802
[AMDGPU] Record old VGPR MSBs in the high bits of s_set_vgpr_msb
rampitec Oct 24, 2025
af9be53
Merge branch 'main' into users/rampitec/10-24-_amdgpu_record_old_vgpr…
rampitec Oct 31, 2025
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16 changes: 13 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ class AMDGPULowerVGPREncoding {
static constexpr unsigned BitsPerField = 2;
static constexpr unsigned NumFields = 4;
static constexpr unsigned FieldMask = (1 << BitsPerField) - 1;
static constexpr unsigned ModeWidth = NumFields * BitsPerField;
static constexpr unsigned ModeMask = (1 << ModeWidth) - 1;
using ModeType = PackedVector<unsigned, BitsPerField,
std::bitset<BitsPerField * NumFields>>;

Expand Down Expand Up @@ -152,13 +154,21 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
CurrentMode |= NewMode;
CurrentMask |= Mask;

MostRecentModeSet->getOperand(0).setImm(CurrentMode);
MachineOperand &Op = MostRecentModeSet->getOperand(0);

// Carry old mode bits from the existing instruction.
int64_t OldModeBits = Op.getImm() & (ModeMask << ModeWidth);

Op.setImm(CurrentMode | OldModeBits);
return true;
}

// Record previous mode into high 8 bits of the immediate.
int64_t OldModeBits = CurrentMode << ModeWidth;

I = handleClause(I);
MostRecentModeSet =
BuildMI(*MBB, I, {}, TII->get(AMDGPU::S_SET_VGPR_MSB)).addImm(NewMode);
MostRecentModeSet = BuildMI(*MBB, I, {}, TII->get(AMDGPU::S_SET_VGPR_MSB))
.addImm(NewMode | OldModeBits);

CurrentMode = NewMode;
CurrentMask = Mask;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
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Expand Up @@ -412,7 +412,7 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
*OutStreamer);

if (isVerbose() && MI->getOpcode() == AMDGPU::S_SET_VGPR_MSB) {
unsigned V = MI->getOperand(0).getImm();
unsigned V = MI->getOperand(0).getImm() & 0xff;
OutStreamer->AddComment(
" msbs: dst=" + Twine(V >> 6) + " src0=" + Twine(V & 3) +
" src1=" + Twine((V >> 2) & 3) + " src2=" + Twine((V >> 4) & 3));
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
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Expand Up @@ -168,7 +168,7 @@ bool AMDGPUMCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,

void AMDGPUMCInstrAnalysis::updateState(const MCInst &Inst, uint64_t Addr) {
if (Inst.getOpcode() == AMDGPU::S_SET_VGPR_MSB_gfx12)
VgprMSBs = Inst.getOperand(0).getImm();
VgprMSBs = Inst.getOperand(0).getImm() & 0xff;
else if (isTerminator(Inst))
VgprMSBs = 0;
}
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250-t16.mir
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Expand Up @@ -36,7 +36,7 @@ body: |
; GCN-NEXT: v_add_f16_e64 v128.l /*v384.l*/, v129.l /*v385.l*/, v130.l /*v386.l*/
$vgpr384_lo16 = V_ADD_F16_t16_e64 0, undef $vgpr385_lo16, 0, undef $vgpr386_lo16, 0, 0, 0, implicit $exec, implicit $mode

; GCN-NEXT: s_set_vgpr_msb 0x8a
; GCN-NEXT: s_set_vgpr_msb 0x458a
; ASM-SAME: ; msbs: dst=2 src0=2 src1=2 src2=0
; GCN-NEXT: v_add_f16_e64 v0.h /*v512.h*/, v1.h /*v513.h*/, v2.h /*v514.h*/
$vgpr512_hi16 = V_ADD_F16_t16_e64 0, undef $vgpr513_hi16, 0, undef $vgpr514_hi16, 0, 0, 0, implicit $exec, implicit $mode
Expand All @@ -50,7 +50,7 @@ body: |
; GCN-NEXT: v_add_f16_e64 v128.l /*v640.l*/, v129.l /*v641.l*/, v130.l /*v642.l*/
$vgpr640_lo16 = V_ADD_F16_t16_e64 0, undef $vgpr641_lo16, 0, undef $vgpr642_lo16, 0, 0, 0, implicit $exec, implicit $mode

; GCN-NEXT: s_set_vgpr_msb 0xcf
; GCN-NEXT: s_set_vgpr_msb 0x8acf
; ASM-SAME: ; msbs: dst=3 src0=3 src1=3 src2=0
; GCN-NEXT: v_add_f16_e64 v0.h /*v768.h*/, v1.h /*v769.h*/, v2.h /*v770.h*/
$vgpr768_hi16 = V_ADD_F16_t16_e64 0, undef $vgpr769_hi16, 0, undef $vgpr770_hi16, 0, 0, 0, implicit $exec, implicit $mode
Expand Down
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