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[AMDGPU] Remove validation of s_set_vgpr_msb range #164888

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Merged
merged 1 commit into from
Oct 23, 2025
Merged

[AMDGPU] Remove validation of s_set_vgpr_msb range #164888

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20 changes: 0 additions & 20 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1860,7 +1860,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
const unsigned CPol);
bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
bool validateSetVgprMSB(const MCInst &Inst, const OperandVector &Operands);
bool validateLdsDirect(const MCInst &Inst, const OperandVector &Operands);
bool validateWMMA(const MCInst &Inst, const OperandVector &Operands);
unsigned getConstantBusLimit(unsigned Opcode) const;
Expand Down Expand Up @@ -5506,22 +5505,6 @@ bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
return true;
}

bool AMDGPUAsmParser::validateSetVgprMSB(const MCInst &Inst,
const OperandVector &Operands) {
if (Inst.getOpcode() != AMDGPU::S_SET_VGPR_MSB_gfx12)
return true;

int Simm16Pos =
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::simm16);
if ((unsigned)Inst.getOperand(Simm16Pos).getImm() > 255) {
SMLoc Loc = Operands[1]->getStartLoc();
Error(Loc, "s_set_vgpr_msb accepts values in range [0..255]");
return false;
}

return true;
}

bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
const OperandVector &Operands) {
unsigned Opc = Inst.getOpcode();
Expand Down Expand Up @@ -5681,9 +5664,6 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, SMLoc IDLoc,
if (!validateTFE(Inst, Operands)) {
return false;
}
if (!validateSetVgprMSB(Inst, Operands)) {
return false;
}
if (!validateWMMA(Inst, Operands)) {
return false;
}
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
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Expand Up @@ -45,6 +45,10 @@ s_set_vgpr_msb 255
// GFX1250: [0xff,0x00,0x86,0xbf]
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU

s_set_vgpr_msb 0xffff
// GFX1250: [0xff,0xff,0x86,0xbf]
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU

s_monitor_sleep 1
// GFX1250: s_monitor_sleep 1 ; encoding: [0x01,0x00,0x84,0xbf]
// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
Expand Down
10 changes: 0 additions & 10 deletions llvm/test/MC/AMDGPU/gfx1250_err.s
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@@ -1,15 +1,5 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX1250-ERR --implicit-check-not=error: -strict-whitespace %s

s_set_vgpr_msb -1
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: s_set_vgpr_msb accepts values in range [0..255]
// GFX1250-ERR: s_set_vgpr_msb -1
// GFX1250-ERR: ^

s_set_vgpr_msb 256
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: s_set_vgpr_msb accepts values in range [0..255]
// GFX1250-ERR: s_set_vgpr_msb 256
// GFX1250-ERR: ^

s_load_b32 s4, s[2:3], 10 th:TH_LOAD_NT th:TH_LOAD_NT
// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// GFX1250-ERR: s_load_b32 s4, s[2:3], 10 th:TH_LOAD_NT th:TH_LOAD_NT
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
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Expand Up @@ -33,6 +33,9 @@
# GFX1250: s_set_vgpr_msb 0xff ; encoding: [0xff,0x00,0x86,0xbf]
0xff,0x00,0x86,0xbf

# GFX1250: s_set_vgpr_msb 0xffff ; encoding: [0xff,0xff,0x86,0xbf]
0xff,0xff,0x86,0xbf

# GFX1250: s_monitor_sleep 0 ; encoding: [0x00,0x00,0x84,0xbf]
0x00,0x00,0x84,0xbf

Expand Down