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[AMDGPU][True16] si-fold-operand selecting srcidx for v_mov_b16_t16_e64 #162101

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[AMDGPU][True16] si-fold-operand selecting srcidx for v_mov_b16_t16_e64 #162101

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63780c2
follow up patch
broxigarchen Oct 6, 2025
ae23434
convert more to static
broxigarchen Oct 15, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -932,7 +932,7 @@ static MachineOperand *lookUpCopyChain(const SIInstrInfo &TII,
for (MachineInstr *SubDef = MRI.getVRegDef(SrcReg);
SubDef && TII.isFoldableCopy(*SubDef);
SubDef = MRI.getVRegDef(Sub->getReg())) {
unsigned SrcIdx = TII.getFoldableCopySrcIdx(*SubDef);
const int SrcIdx = SubDef->getOpcode() == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
MachineOperand &SrcOp = SubDef->getOperand(SrcIdx);

if (SrcOp.isImm())
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35 changes: 5 additions & 30 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3411,7 +3411,6 @@ void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::V_MOV_B16_t16_e32:
case AMDGPU::V_MOV_B16_t16_e64:
case AMDGPU::V_MOV_B32_e32:
case AMDGPU::V_MOV_B32_e64:
case AMDGPU::V_MOV_B64_PSEUDO:
Expand All @@ -3428,34 +3427,10 @@ bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
case AMDGPU::AV_MOV_B32_IMM_PSEUDO:
case AMDGPU::AV_MOV_B64_IMM_PSEUDO:
return true;
default:
return false;
}
}

unsigned SIInstrInfo::getFoldableCopySrcIdx(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::V_MOV_B16_t16_e32:
case AMDGPU::V_MOV_B16_t16_e64:
return 2;
case AMDGPU::V_MOV_B32_e32:
case AMDGPU::V_MOV_B32_e64:
case AMDGPU::V_MOV_B64_PSEUDO:
case AMDGPU::V_MOV_B64_e32:
case AMDGPU::V_MOV_B64_e64:
case AMDGPU::S_MOV_B32:
case AMDGPU::S_MOV_B64:
case AMDGPU::S_MOV_B64_IMM_PSEUDO:
case AMDGPU::COPY:
case AMDGPU::WWM_COPY:
case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
case AMDGPU::V_ACCVGPR_READ_B32_e64:
case AMDGPU::V_ACCVGPR_MOV_B32:
case AMDGPU::AV_MOV_B32_IMM_PSEUDO:
case AMDGPU::AV_MOV_B64_IMM_PSEUDO:
return 1;
return !hasAnyModifiersSet(MI);
default:
llvm_unreachable("MI is not a foldable copy");
return false;
}
}

Expand Down Expand Up @@ -4715,12 +4690,12 @@ bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
}

bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
AMDGPU::OpName OpName) const {
AMDGPU::OpName OpName) {
const MachineOperand *Mods = getNamedOperand(MI, OpName);
return Mods && Mods->getImm();
}

bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {
bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) {
return any_of(ModifierOpNames,
[&](AMDGPU::OpName Name) { return hasModifiersSet(MI, Name); });
}
Expand Down Expand Up @@ -9362,7 +9337,7 @@ Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
}

MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
AMDGPU::OpName OperandName) const {
AMDGPU::OpName OperandName) {
if (OperandName == AMDGPU::OpName::NUM_OPERAND_NAMES)
return nullptr;

Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1254,8 +1254,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// e.g. src[012]_mod, omod, clamp.
bool hasModifiers(unsigned Opcode) const;

bool hasModifiersSet(const MachineInstr &MI, AMDGPU::OpName OpName) const;
bool hasAnyModifiersSet(const MachineInstr &MI) const;
static bool hasModifiersSet(const MachineInstr &MI, AMDGPU::OpName OpName);
static bool hasAnyModifiersSet(const MachineInstr &MI);

bool canShrink(const MachineInstr &MI,
const MachineRegisterInfo &MRI) const;
Expand Down Expand Up @@ -1431,12 +1431,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// Returns the operand named \p Op. If \p MI does not have an
/// operand named \c Op, this function returns nullptr.
LLVM_READONLY
MachineOperand *getNamedOperand(MachineInstr &MI,
AMDGPU::OpName OperandName) const;
static MachineOperand *getNamedOperand(MachineInstr &MI,
AMDGPU::OpName OperandName);

LLVM_READONLY
const MachineOperand *getNamedOperand(const MachineInstr &MI,
AMDGPU::OpName OperandName) const {
static const MachineOperand *getNamedOperand(const MachineInstr &MI,
AMDGPU::OpName OperandName) {
return getNamedOperand(const_cast<MachineInstr &>(MI), OperandName);
}

Expand Down
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