[PowerPC] Implement AES Acceleration Instructions #157725
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Member
|
@llvm/pr-subscribers-backend-powerpc Author: Lei Huang (lei137) ChangesImplement AES Acceleration Instructions:
Full diff: https://github.com/llvm/llvm-project/pull/157725.diff 4 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index a12dfae2a0d7f..25ec35925c24c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -120,6 +120,74 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Inst{21...31} = xo;
}
+class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+ bits<5> XTp;
+ bits<5> XBp;
+ bits<2> M;
+
+ let Pattern = pattern;
+
+ let Inst{6...9} = XTp{3...0};
+ let Inst {10} = XTp{4};
+ let Inst{15} = M{0};
+ let Inst{16...19} = XBp{3...0};
+ let Inst{20} = M{1};
+ let Inst{21...29} = xo;
+ let Inst{30} = XBp{4};
+}
+
+class XX3Form_XTABp5_M2<bits<8> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+ bits<5> XTp;
+ bits<5> XAp;
+ bits<5> XBp;
+ bits<2> M;
+
+ let Pattern = pattern;
+
+ let Inst{6...9} = XTp{3...0};
+ let Inst{10} = XTp{4};
+ let Inst{11...14} = XAp{3...0};
+ let Inst{15} = M{0};
+ let Inst{16...19} = XBp{3...0};
+ let Inst{20} = M{1};
+ let Inst{21...28} = xo;
+ let Inst{29} = XAp{4};
+ let Inst{30} = XBp{4};
+}
+
+class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<60, OOL, IOL, asmstr, NoItinerary> {
+
+ bits<6> XT;
+ bits<6> XA;
+ bits<6> XB;
+ bits<1> P;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...22} = 3;
+ let Inst{23} = P;
+ let Inst{24...28} = xo;
+ let Inst{29} = XA{5};
+ let Inst{30} = XB{5};
+ let Inst{31} = XT{5};
+}
+
+//-------------------------- Instruction definitions -------------------------//
+// Predicate combinations available:
+// [IsISAFuture]
+// [HasVSX, IsISAFuture]
+
let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
@@ -191,4 +259,51 @@ let Predicates = [HasVSX, IsISAFuture] in {
def VUCMPRLH
: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprlh $VRT, $VRA, $VRB", []>;
+
+ // AES Acceleration Instructions
+ def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp),
+ (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
+ "xxaesencp $XTp, $XAp, $XBp, $M", []>;
+ def XXAESDECP : XX3Form_XTABp5_M2<202, (outs vsrprc:$XTp),
+ (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
+ "xxaesdecp $XTp, $XAp, $XBp, $M", []>;
+ def XXAESGENLKP : XX3Form_XTBp5_M2<420, (outs vsrprc:$XTp),
+ (ins vsrprc:$XBp, u2imm:$M),
+ "xxaesgenlkp $XTp, $XBp, $M", []>;
+ def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT),
+ (ins vsrc:$XA, vsrc:$XB, u1imm:$P),
+ "xxgfmul128 $XT, $XA, $XB, $P", []>;
+}
+
+//---------------------------- Anonymous Patterns ----------------------------//
+// Predicate combinations available:
+
+
+//---------------------------- Instruction aliases ---------------------------//
+// Predicate combinations available:
+// [HasVSX, IsISAFuture]
+
+let Predicates = [HasVSX, IsISAFuture] in {
+ def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp",
+ (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
+ def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp",
+ (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
+ def : InstAlias<"xxaes256encp $XTp, $XAp, $XBp",
+ (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
+ def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp",
+ (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
+ def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp",
+ (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
+ def : InstAlias<"xxaes256decp $XTp, $XAp, $XBp",
+ (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
+ def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
+ vsrprc:$XBp, 0)>;
+ def : InstAlias<"xxaes192genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
+ vsrprc:$XBp, 1)>;
+ def : InstAlias<"xxaes256genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
+ vsrprc:$XBp, 2)>;
+ def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
+ vsrc:$XB, 0)>;
+ def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
+ vsrc:$XB, 1)>;
}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index da3601b00b199..a203c706fb44a 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -231,3 +231,15 @@
#CHECK: vucmprhh 1, 3, 6
0x10,0x23,0x31,0x03
+
+#CHECK: xxaes192encp 8, 10, 14
+0xf1,0x0b,0x76,0x10
+
+#CHECK: xxaes256decp 14, 10, 6
+0xf1,0xca,0x3e,0x50
+
+#CHECK: xxaes128genlkp 4, 8
+0xf0,0x80,0x46,0x90
+
+#CHECK: xxgfmul128gcm 7, 5, 4
+0xf0,0xe5,0x26,0xd0
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 66d05043301b6..713015df90b91 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -225,3 +225,15 @@
#CHECK: vucmprhh 1, 3, 6
0x03,0x31,0x23,0x10
+
+#CHECK: xxaes192encp 8, 10, 14
+0x10,0x76,0x0b,0xf1
+
+#CHECK: xxaes256decp 14, 10, 6
+0x50,0x3e,0xca,0xf1
+
+#CHECK: xxaes128genlkp 4, 8
+0x90,0x46,0x80,0xf0
+
+#CHECK: xxgfmul128gcm 7, 5, 4
+0xd0,0x26,0xe5,0xf0
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 6ae7bd785773d..824716877d57f 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -330,3 +330,19 @@
vucmprhh 1, 3, 6
#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03]
#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10]
+
+ xxaes192encp 8, 10, 14
+#CHECK-BE: xxaes192encp 8, 10, 14 # encoding: [0xf1,0x0b,0x76,0x10]
+#CHECK-LE: xxaes192encp 8, 10, 14 # encoding: [0x10,0x76,0x0b,0xf1]
+
+ xxaes256decp 14, 10, 6
+#CHECK-BE: xxaes256decp 14, 10, 6 # encoding: [0xf1,0xca,0x3e,0x50]
+#CHECK-LE: xxaes256decp 14, 10, 6 # encoding: [0x50,0x3e,0xca,0xf1]
+
+ xxaes128genlkp 4, 8
+#CHECK-BE: xxaes128genlkp 4, 8 # encoding: [0xf0,0x80,0x46,0x90]
+#CHECK-LE: xxaes128genlkp 4, 8 # encoding: [0x90,0x46,0x80,0xf0]
+
+ xxgfmul128gcm 7, 5, 4
+#CHECK-BE: xxgfmul128gcm 7, 5, 4 # encoding: [0xf0,0xe5,0x26,0xd0]
+#CHECK-LE: xxgfmul128gcm 7, 5, 4 # encoding: [0xd0,0x26,0xe5,0xf0]
|
Implement AES Acceleration Instructions: * xxaesencp * xxaesdecp * xxaesgenlkp * xxgfmul128
lei137
force-pushed
the
AESAcceleration
branch
from
a203fba to
ccc7be7
Compare
maryammo
reviewed
Sep 19, 2025
| //-------------------------- Instruction definitions -------------------------// | ||
| // Predicate combinations available: | ||
| // [IsISAFuture] | ||
| // [HasVSX, IsISAFuture] |
Contributor
There was a problem hiding this comment.
These AES instructions use VSX registers, so do we need HasVSX predicate?
Contributor
Author
There was a problem hiding this comment.
I am not sure I understand the questions... They do use them therefore I think it is needed.
The instructions are currently defined under the predicate combinations: [HasVSX, IsISAFuture] as are the aliases.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Implement AES Acceleration Instructions: