[AMDGPU] Add documentation files for GFX12.

llvm/docs/AMDGPU/gfx12_addr.rst

@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_addr:
+
+addr
+====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_attr.rst

@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_attr:
+
+attr
+====
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+    ds_param_load v1, attr0.x

llvm/docs/AMDGPU/gfx12_clause.rst

@@ -0,0 +1,7 @@
+.. _amdgpu_synid_clause:
+
+clause
+======
+
+Description of a clause following this instruction.
+

llvm/docs/AMDGPU/gfx12_data0_56f215.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_56f215:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data0_6802ce.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_6802ce:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data0_e016a1.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_e016a1:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data0_fd235e.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_fd235e:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data1_6802ce.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_6802ce:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data1_731030.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_731030:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data1_e016a1.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_e016a1:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_data1_fd235e.rst

@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_fd235e:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`

llvm/docs/AMDGPU/gfx12_delay.rst

@@ -0,0 +1,74 @@
+.. _amdgpu_synid_delay:
+
+delay
+=====
+
+A delay between dependent SALU/VALU instructions.
+This operand may specify a delay for 2 instructions:
+the one after the current *s_delay_alu* instruction
+and for the second instruction indicated by *SKIP*.
+
+The bits of this operand have the following meaning:
+
+    ===== ========================================================== ============
+    Bits  Description                                                Value Range
+    ===== ========================================================== ============
+    3:0   ID0: indicates a delay for the first instruction.          0..11
+    6:4   SKIP: indicates the position of the second instruction.    0..5
+    10:7  ID1: indicates a delay for the second instruction.         0..11
+    ===== ========================================================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *instid0*, *instskip*, *instid1* values described below.
+
+    ======================== =========================== ===============
+    Syntax                   Description                 Default Value
+    ======================== =========================== ===============
+    instid0(<*ID name*>)     A symbolic *ID0* value.     instid0(NO_DEP)
+    instskip(<*SKIP name*>)  A symbolic *SKIP* value.    instskip(SAME)
+    instid1(<*ID name*>)     A symbolic *ID1* value.     instid1(NO_DEP)
+    ======================== =========================== ===============
+
+These values may be specified in any order.
+When more than one value is specified, the values must be separated from each other by a '|'.
+
+Valid *ID names* are defined below.
+
+    =================== ===================================================================
+    Name                Description
+    =================== ===================================================================
+    NO_DEP              No dependency on any prior instruction. This is the default value.
+    VALU_DEP_1          Dependency on a previous VALU instruction, 1 opcode back.
+    VALU_DEP_2          Dependency on a previous VALU instruction, 2 opcodes back.
+    VALU_DEP_3          Dependency on a previous VALU instruction, 3 opcodes back.
+    VALU_DEP_4          Dependency on a previous VALU instruction, 4 opcodes back.
+    TRANS32_DEP_1       Dependency on a previous TRANS32 instruction, 1 opcode back.
+    TRANS32_DEP_2       Dependency on a previous TRANS32 instruction, 2 opcodes back.
+    TRANS32_DEP_3       Dependency on a previous TRANS32 instruction, 3 opcodes back.
+    FMA_ACCUM_CYCLE_1   Single cycle penalty for FMA accumulation.
+    SALU_CYCLE_1        1 cycle penalty for a prior SALU instruction.
+    SALU_CYCLE_2        2 cycle penalty for a prior SALU instruction.
+    SALU_CYCLE_3        3 cycle penalty for a prior SALU instruction.
+    =================== ===================================================================
+
+Legal *SKIP names* are described in the following table.
+
+    ======== ============================================================================
+    Name     Description
+    ======== ============================================================================
+    SAME     Apply second dependency to the same instruction. This is the default value.
+    NEXT     Apply second dependency to the next instruction.
+    SKIP_1   Skip 1 instruction then apply dependency.
+    SKIP_2   Skip 2 instructions then apply dependency.
+    SKIP_3   Skip 3 instructions then apply dependency.
+    SKIP_4   Skip 4 instructions then apply dependency.
+    ======== ============================================================================
+
+Examples:
+
+.. parsed-literal::
+
+    s_delay_alu instid0(VALU_DEP_1)
+    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)

llvm/docs/AMDGPU/gfx12_hwreg.rst

@@ -0,0 +1,76 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_hwreg:
+
+hwreg
+=====
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ======= ===================== ============
+    Bits    Description           Value Range
+    ======= ===================== ============
+    5:0     Register *id*.        0..63
+    10:6    First bit *offset*.   0..31
+    15:11   *Size* in bits.       1..32
+    ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+    ==================================== ============================================================================
+    Hwreg Value Syntax                   Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID1       Id of wave, simd, compute unit, etc.
+    HW_REG_HW_ID2       Id of queue, pipeline, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES Memory aperture.
+    HW_REG_FLAT_SCR_LO  flat_scratch_lo register.
+    HW_REG_FLAT_SCR_HI  flat_scratch_hi register.
+    =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+    reg = 1
+    offset = 2
+    size = 4
+    hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+    s_getreg_b32 s2, 0x1881
+    s_getreg_b32 s2, hwreg_enc                     // the same as above
+    s_getreg_b32 s2, hwreg(1, 2, 4)                // the same as above
+    s_getreg_b32 s2, hwreg(reg, offset, size)      // the same as above
+
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

llvm/docs/AMDGPU/gfx12_imm16.rst

@@ -0,0 +1,7 @@
+.. _amdgpu_synid_imm16:
+
+imm16
+======
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+

llvm/docs/AMDGPU/gfx12_ioffset.rst

@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ioffset:
+
+ioffset
+=======
+
+*Size:* 1 dword.
+
+*Operands:*