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[SelectionDAG][ARM] Propagate fast math flags in visitBRCOND #156647

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Merged
merged 4 commits into from
Sep 6, 2025
Merged

[SelectionDAG][ARM] Propagate fast math flags in visitBRCOND #156647

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c1b9fbf
[SelectionDAG][ARM] Propagate fast math flags in visitBRCOND
paperchalice Sep 3, 2025
91c8ee3
format
paperchalice Sep 4, 2025
9c92aed
update test
paperchalice Sep 4, 2025
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Move out flags
paperchalice Sep 4, 2025
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8 changes: 4 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19341,13 +19341,13 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
// MachineBasicBlock CFG, which is awkward.

// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
// on the target, also copy fast math flags.
if (N1.getOpcode() == ISD::SETCC &&
TLI.isOperationLegalOrCustom(ISD::BR_CC,
N1.getOperand(0).getValueType())) {
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, Chain,
N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2,
N1->getFlags());
}

if (N1.hasOneUse()) {
Expand Down
11 changes: 7 additions & 4 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -5570,7 +5570,7 @@ static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
llvm_unreachable("Unknown VFP cmp argument!");
}

/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
/// OptimizeVFPBrcond - With nnan, it's legal to optimize some
/// f32 and even f64 comparisons to integer ones.
SDValue
ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
Expand Down Expand Up @@ -5712,9 +5712,12 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, Cmp);
}

if (getTargetMachine().Options.UnsafeFPMath &&
(CC == ISD::SETEQ || CC == ISD::SETOEQ ||
CC == ISD::SETNE || CC == ISD::SETUNE)) {
SDNodeFlags Flags = Op->getFlags();
if ((getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
(DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
(CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
CC == ISD::SETUNE)) {
if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
return Result;
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/fpcmp-opt.ll
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@@ -1,4 +1,4 @@
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 %s -o - \
; RUN: | FileCheck %s

; rdar://7461510
Expand Down Expand Up @@ -42,7 +42,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load double, ptr %a
%1 = fcmp oeq double %0, 0.000000e+00
%1 = fcmp nnan oeq double %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2

bb1:
Expand All @@ -65,7 +65,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load float, ptr %a
%1 = fcmp oeq float %0, 0.000000e+00
%1 = fcmp nnan oeq float %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2

bb1:
Expand Down