[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. #155747

ukalappa-mips · 2025-08-28T04:56:10Z

Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information .

and files like RISCVInstrInfoXMips.td clang formatted .

No Regression found.

Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information . and files like RISCVInstrInfoXMips.td clang formatted . No Regression found.

llvmbot · 2025-08-28T04:56:42Z

@llvm/pr-subscribers-clang
@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-backend-mips

Author: UmeshKalappa (ukalappa-mips)

Changes

Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information .

and files like RISCVInstrInfoXMips.td clang formatted .

No Regression found.

Full diff: https://github.com/llvm/llvm-project/pull/155747.diff

8 Files Affected:

(modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+8-7)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+9-2)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+158-80)
(modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+2-1)
(modified) llvm/test/CodeGen/RISCV/features-info.ll (+1)
(modified) llvm/test/MC/RISCV/xmips-invalid.s (+10-1)
(modified) llvm/test/MC/RISCV/xmips-valid.s (+21-3)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1)

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index dbb16fce8390a..de1bdb4a8811c 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -656,6 +656,13 @@ static constexpr FeatureBitset XSfSystemGroup = {
     RISCV::FeatureVendorXSiFivecflushdlone,
 };
 
+static constexpr FeatureBitset XMIPSGroup = {
+    RISCV::FeatureVendorXMIPSLSP,
+    RISCV::FeatureVendorXMIPSCMov,
+    RISCV::FeatureVendorXMIPSCBOP,
+    RISCV::FeatureVendorXMIPSEXECTL,
+};
+
 static constexpr FeatureBitset XTHeadGroup = {
     RISCV::FeatureVendorXTHeadBa,      RISCV::FeatureVendorXTHeadBb,
     RISCV::FeatureVendorXTHeadBs,      RISCV::FeatureVendorXTHeadCondMov,
@@ -684,13 +691,7 @@ static constexpr DecoderListEntry DecoderList32[]{
     {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
     {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
     {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
-    {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
-    {DecoderTableXmipscmov32,
-     {RISCV::FeatureVendorXMIPSCMov},
-     "MIPS mips.ccmov"},
-    {DecoderTableXmipscbop32,
-     {RISCV::FeatureVendorXMIPSCBOP},
-     "MIPS mips.pref"},
+    {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
     {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     // Standard Extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3b738e4cc11a1..13e3b1b0d45de 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1396,20 +1396,27 @@ def HasVendorXMIPSCMov
       AssemblerPredicate<(all_of FeatureVendorXMIPSCMov),
                          "'Xmipscmov' ('mips.ccmov' instruction)">;
 def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+
 def FeatureVendorXMIPSLSP
     : RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
 def HasVendorXMIPSLSP
     : Predicate<"Subtarget->hasVendorXMIPSLSP()">,
       AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
                          "'Xmipslsp' (load and store pair instructions)">;
-def FeatureVendorXMIPSCBOP
-    : RISCVExtension<1, 0, "MIPS Software Prefetch">;
+
+def FeatureVendorXMIPSCBOP : RISCVExtension<1, 0, "MIPS Software Prefetch">;
 def HasVendorXMIPSCBOP
     : Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
       AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
                          "'Xmipscbop' (MIPS hardware prefetch)">;
 def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
 
+def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS extensions">;
+def HasVendorXMIPSEXECTL
+    : Predicate<"Subtarget->hasVendorXMIPSEXT()">,
+      AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),
+                         "'Xmipsexectl' (Mips extensions)">;
+
 // WCH / Nanjing Qinheng Microelectronics Extension(s)
 
 def FeatureVendorXwchc
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
index 889ea98022572..0d1999f329234 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -47,13 +47,13 @@ class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rd1;
   bits<5> rd2;
 
-  let Inst{31-27} = rd2;
-  let Inst{26-23} = imm7{6-3};
-  let Inst{22-20} = 0b000;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b100;
-  let Inst{11-7} = rd1;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rd2;
+  let Inst{26 - 23} = imm7{6 - 3};
+  let Inst{22 - 20} = 0b000;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b100;
+  let Inst{11 - 7} = rd1;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Load word pair format.
@@ -64,13 +64,13 @@ class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rd1;
   bits<5> rd2;
 
-  let Inst{31-27} = rd2;
-  let Inst{26-22} = imm7{6-2};
-  let Inst{21-20} = 0b01;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b100;
-  let Inst{11-7} = rd1;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rd2;
+  let Inst{26 - 22} = imm7{6 - 2};
+  let Inst{21 - 20} = 0b01;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b100;
+  let Inst{11 - 7} = rd1;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Store double pair format.
@@ -81,14 +81,14 @@ class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rs2;
   bits<5> rs1;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = imm7{6-5};
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b101;
-  let Inst{11-10} = imm7{4-3};
-  let Inst{9-7} = 0b000;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rs3;
+  let Inst{26 - 25} = imm7{6 - 5};
+  let Inst{24 - 20} = rs2;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b101;
+  let Inst{11 - 10} = imm7{4 - 3};
+  let Inst{9 - 7} = 0b000;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Store word pair format.
@@ -99,89 +99,167 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
   bits<5> rs2;
   bits<5> rs1;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = imm7{6-5};
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b101;
-  let Inst{11-9} = imm7{4-2};
-  let Inst{8-7} = 0b01;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 27} = rs3;
+  let Inst{26 - 25} = imm7{6 - 5};
+  let Inst{24 - 20} = rs2;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b101;
+  let Inst{11 - 9} = imm7{4 - 2};
+  let Inst{8 - 7} = 0b01;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
 }
 
 // Prefetch format.
-let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
-class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
+let hasSideEffects = 0, mayLoad = 1,
+    mayStore = 1 in class
+        Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<9> imm9;
   bits<5> rs1;
   bits<5> hint;
 
-  let Inst{31-29} = 0b000;
-  let Inst{28-20} = imm9;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = 0b000;
-  let Inst{11-7} = hint;
-  let Inst{6-0} = OPC_CUSTOM_0.Value;
+  let Inst{31 - 29} = 0b000;
+  let Inst{28 - 20} = imm9;
+  let Inst{19 - 15} = rs1;
+  let Inst{14 - 12} = 0b000;
+  let Inst{11 - 7} = hint;
+  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
+}
+
+// MIPS Ext Insns
+let hasSideEffects = 1, mayLoad = 0,
+    mayStore = 0 in class MIPSExtInst_ri<bits<6> shimm5, string opcodestr>
+    : RVInstIShift<0b00000, 0b001, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
+  let shamt = shimm5;
+  let rd = 0;
+  let rs1 = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // MIPS extensions
 //===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
-  def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
-                                    "mips.pref", "$hint, ${imm9}(${rs1})">,
-                   Sched<[]>;
+let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
+  def MIPS_PREF : Mips_prefetch_ri<(outs),
+                                   (ins GPR
+                                    : $rs1, uimm9
+                                    : $imm9, uimm5
+                                    : $hint),
+                                   "mips.pref", "$hint, ${imm9}(${rs1})">,
+                  Sched<[]>;
+}
+
+let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in {
+  def MIPS_EHB : MIPSExtInst_ri<0b000011, "mips.ehb">;
+  def MIPS_IHB : MIPSExtInst_ri<0b000001, "mips.ihb">;
+  def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;
 }
 
 let Predicates = [HasVendorXMIPSCBOP] in {
   // Prefetch Data Write.
-  def : Pat<(prefetch (AddrRegImm9  (XLenVT GPR:$rs1), uimm9:$imm9),
+  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR
+                                  : $rs1),
+                      uimm9
+                      : $imm9),
              (i32 1), timm, (i32 1)),
-            (MIPS_PREF GPR:$rs1, uimm9:$imm9, 9)>;
+            (MIPS_PREF GPR
+             : $rs1, uimm9
+             : $imm9, 9)>;
   // Prefetch Data Read.
-  def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
+  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR
+                                  : $rs1),
+                      uimm9
+                      : $imm9),
              (i32 0), timm, (i32 1)),
-            (MIPS_PREF GPR:$rs1, uimm9:$imm9, 8)>;
+            (MIPS_PREF GPR
+             : $rs1, uimm9
+             : $imm9, 8)>;
 }
 
-let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
-                 DecoderNamespace = "Xmipscmov" in {
-def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
-                          (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
-                          "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
-                 Sched<[]>;
+let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0, DecoderNamespace = "XMIPS" in {
+  def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0,
+                            (outs GPR
+                             : $rd),
+                            (ins GPR
+                             : $rs1, GPR
+                             : $rs2, GPR
+                             : $rs3),
+                            "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+                   Sched<[]>;
 }
 
 let Predicates = [UseCCMovInsn] in {
-def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),
-                  (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(select (riscv_seteq (XLenVT GPR:$rs2)),
-                  (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-
-def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
-          (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+  def : Pat<(select(riscv_setne(XLenVT GPR
+                                : $rs2)),
+             (XLenVT GPR
+              : $rs1),
+             (XLenVT GPR
+              : $rs3)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
+  def : Pat<(select(riscv_seteq(XLenVT GPR
+                                : $rs2)),
+             (XLenVT GPR
+              : $rs3),
+             (XLenVT GPR
+              : $rs1)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
+
+  def : Pat<(select(XLenVT GPR
+                    : $rs2),
+             (XLenVT GPR
+              : $rs1),
+             (XLenVT GPR
+              : $rs3)),
+            (MIPS_CCMOV GPR
+             : $rs1, GPR
+             : $rs2, GPR
+             : $rs3)>;
 }
 
 let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,
-                 DecoderNamespace = "Xmipslsp" in {
-let mayLoad = 1, mayStore = 0 in {
-def MIPS_LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
-                         "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
-               Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
-def MIPS_LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),
-                         "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
-               Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
-} // mayLoad = 1, mayStore = 0
-
-let mayLoad = 0, mayStore = 1 in {
-def MIPS_SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),
-                         "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
-               Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;
-def MIPS_SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),
-                         "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
-               Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;
-} // mayLoad = 0, mayStore = 1
-} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace = "Xmipslsp"
+    DecoderNamespace = "XMIPS" in {
+  let mayLoad = 1, mayStore = 0 in {
+    def MIPS_LWP : LWPFormat<(outs GPR
+                              : $rd1, GPR
+                              : $rd2),
+                             (ins GPR
+                              : $rs1, uimm7_lsb00
+                              : $imm7),
+                             "mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+                   Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
+    def MIPS_LDP : LDPFormat<(outs GPR
+                              : $rd1, GPR
+                              : $rd2),
+                             (ins GPR
+                              : $rs1, uimm7_lsb000
+                              : $imm7),
+                             "mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
+                   Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
+  } // mayLoad = 1, mayStore = 0
+
+  let mayLoad = 0, mayStore = 1 in {
+    def MIPS_SWP : SWPFormat<(outs),
+                             (ins GPR
+                              : $rs2, GPR
+                              : $rs3, GPR
+                              : $rs1, uimm7_lsb00
+                              : $imm7),
+                             "mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
+                   Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]>;
+    def MIPS_SDP : SDPFormat<(outs),
+                             (ins GPR
+                              : $rs2, GPR
+                              : $rs3, GPR
+                              : $rs1, uimm7_lsb000
+                              : $imm7),
+                             "mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
+                   Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;
+  } // mayLoad = 0, mayStore = 1
+} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace =
+  // "XMIPS"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index f89d94f41b69f..7ef11bd32ca12 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -121,7 +121,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
                                       FeatureStdExtZicsr,
                                       FeatureVendorXMIPSCMov,
                                       FeatureVendorXMIPSLSP,
-                                      FeatureVendorXMIPSCBOP],
+                                      FeatureVendorXMIPSCBOP,
+				      FeatureVendorXMIPSEXECTL],
                                      [TuneMIPSP8700]>;
 
 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index f966f800589b7..9999032762811 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -198,6 +198,7 @@
 ; CHECK-NEXT:   xcvsimd                          - 'XCVsimd' (CORE-V SIMD ALU).
 ; CHECK-NEXT:   xmipscbop                        - 'XMIPSCBOP' (MIPS Software Prefetch).
 ; CHECK-NEXT:   xmipscmov                        - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
+; CHECK-NEXT:   mipsexectl                       - 'XMIPSEXECTL' (MIPS extensions).
 ; CHECK-NEXT:   xmipslsp                         - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
 ; CHECK-NEXT:   xsfcease                         - 'XSfcease' (SiFive sf.cease Instruction).
 ; CHECK-NEXT:   xsfmm128t                        - 'XSfmm128t' (TE=128 configuration).
diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
index a17d2e347f8d9..b63e3a8bdcdf1 100644
--- a/llvm/test/MC/RISCV/xmips-invalid.s
+++ b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,5 +1,14 @@
 # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
-# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+Xmipscbop < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s 2>&1 | FileCheck %s
+
+mips.pause 10
+# CHECK: error: invalid operand for instruction
+
+mips.ehb 10
+# CHECK: error: invalid operand for instruction 
+
+mips.ihb 10
+# CHECK: error: invalid operand for instruction
 
 mips.pref   8, 512(a0)
 # CHECK: error: immediate offset must be in the range [0, 511]
diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s
index c5755ee81b499..1c193e610d247 100644
--- a/llvm/test/MC/RISCV/xmips-valid.s
+++ b/llvm/test/MC/RISCV/xmips-valid.s
@@ -1,9 +1,27 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+Xmipscmov,+xmipscbop,+xmipsexectl  -M no-aliases -show-encoding \
 # RUN:   | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop < %s \
-# RUN:   | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s \
+# RUN:   | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl -M no-aliases -d - \
 # RUN:   | FileCheck -check-prefix=CHECK-DIS %s
 
+# CHECK-INST: mips.pause
+# CHECK-ENC:  encoding: [0x13,0x10,0x50,0x00]
+mips.pause
+
+# CHECK-DIS: mips.pause
+
+# CHECK-INST: mips.ehb
+# CHECK-ENC:  encoding: [0x13,0x10,0x30,0x00]
+mips.ehb
+
+# CHECK-DIS: mips.ehb
+
+# CHECK-INST: mips.ihb
+# CHECK-ENC:  encoding: [0x13,0x10,0x10,0x00]
+mips.ihb
+
+# CHECK-DIS: mips.ihb
+
 # CHECK-INST: mips.pref 8, 511(a0)
 # CHECK-ENC:  encoding: [0x0b,0x04,0xf5,0x1f]
 mips.pref	8, 511(a0)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 9cee4ff776da9..1ece678a464ff 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1146,6 +1146,7 @@ R"(All available -march extensions for RISC-V
     xcvsimd              1.0
     xmipscbop            1.0
     xmipscmov            1.0
+    xmipsexectl          1.0
     xmipslsp             1.0
     xsfcease             1.0
     xsfmm128t            0.6

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

llvm/lib/Target/RISCV/RISCVProcessors.td

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

llvm/test/MC/RISCV/xmips-valid.s

Co-authored-by: Craig Topper <[email protected]>

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

llvm/lib/Target/RISCV/RISCVFeatures.td

Co-authored-by: Craig Topper <[email protected]>

ukalappa-mips · 2025-08-30T07:16:01Z

@topperc ,is that ok to commit ?

topperc

LGTM

the following changes are made a)Typo Fix (with previous PRhttps://github.com//pull/155747) b)builtins support for MIPS P8700 execution control instructions . c)Testcase

…trol . the following changes are made a)Typo Fix (with previous PRhttps://github.com/llvm/llvm-project/pull/155747) b)builtins support for MIPS P8700 execution control instructions . c)Testcase

Added the mips extension instructions like ehb,ihb and pause etc.

7dca481

Please refer the https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf for more information . and files like RISCVInstrInfoXMips.td clang formatted . No Regression found.

llvmbot added backend:MIPS backend:RISC-V labels Aug 28, 2025

ukalappa-mips changed the title ~~Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700~~ [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700 Aug 28, 2025

ukalappa-mips changed the title ~~[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700~~ [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700. Aug 28, 2025

topperc reviewed Aug 28, 2025

View reviewed changes

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td Outdated Show resolved Hide resolved

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td Outdated Show resolved Hide resolved

llvmbot added clang Clang issues not falling into any other category clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Aug 28, 2025

Reformatted changes with clang-format and testcase fix.

0f8330a

ukalappa-mips force-pushed the ukalappa_xmipsextn branch from d4daf57 to 0f8330a Compare August 28, 2025 10:26

ukalappa-mips changed the title ~~[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700.~~ [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc forMIPS RV64 P8700. Aug 28, 2025

ukalappa-mips changed the title ~~[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc forMIPS RV64 P8700.~~ [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. Aug 28, 2025

topperc reviewed Aug 28, 2025

View reviewed changes

ukalappa-mips and others added 4 commits August 29, 2025 09:18

Update llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

4f1d89b

Co-authored-by: Craig Topper <[email protected]>

Update llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

f7b5025

Co-authored-by: Craig Topper <[email protected]>

Update llvm/test/MC/RISCV/xmips-valid.s

dd0e158

Co-authored-by: Craig Topper <[email protected]>

Updated the code to address the comments

3d8f1d1

topperc reviewed Aug 29, 2025

View reviewed changes

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td Outdated Show resolved Hide resolved

llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td Outdated Show resolved Hide resolved

llvm/lib/Target/RISCV/RISCVFeatures.td Outdated Show resolved Hide resolved

ukalappa-mips and others added 2 commits August 29, 2025 12:21

Update llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

1b6005d

Co-authored-by: Craig Topper <[email protected]>

Update llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

50aac43

Co-authored-by: Craig Topper <[email protected]>

ukalappa-mips force-pushed the ukalappa_xmipsextn branch from 78c416a to f9e72b8 Compare August 29, 2025 07:19

Updated the extension description and testcase updated for the same

43209ae

ukalappa-mips force-pushed the ukalappa_xmipsextn branch from f9e72b8 to 43209ae Compare August 29, 2025 07:20

Merge branch 'main' into ukalappa_xmipsextn

5f6d7ab

topperc approved these changes Aug 30, 2025

View reviewed changes

djtodoro merged commit 1debf23 into llvm:main Sep 1, 2025
9 checks passed

s-barannikov mentioned this pull request Sep 1, 2025

[TableGen][Decoder] Decode operands with zero width or all bits known #156358

Merged

ukalappa-mips mentioned this pull request Sep 17, 2025

RISCV: the builtins support for MIPS RV64 P8700 execution control . #159246

Merged

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. #155747

[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. #155747

Uh oh!

ukalappa-mips commented Aug 28, 2025

Uh oh!

llvmbot commented Aug 28, 2025 •

edited

Loading

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

ukalappa-mips commented Aug 30, 2025

Uh oh!

topperc left a comment

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. #155747

[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. #155747

Uh oh!

Conversation

ukalappa-mips commented Aug 28, 2025

Uh oh!

llvmbot commented Aug 28, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

ukalappa-mips commented Aug 30, 2025

Uh oh!

topperc left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

llvmbot commented Aug 28, 2025 •

edited

Loading