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AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks #154501

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Merged
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Aug 26, 2025
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AMDGPU: Replace copy-to-mov-imm folding logic with class compat checks #154501

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85 changes: 51 additions & 34 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1248,6 +1248,7 @@ void SIFoldOperandsImpl::foldOperand(
if (FoldingImmLike && UseMI->isCopy()) {
Register DestReg = UseMI->getOperand(0).getReg();
Register SrcReg = UseMI->getOperand(1).getReg();
unsigned UseSubReg = UseMI->getOperand(1).getSubReg();
assert(SrcReg.isVirtual());

const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg);
Expand Down Expand Up @@ -1278,44 +1279,60 @@ void SIFoldOperandsImpl::foldOperand(
DestRC = &AMDGPU::SGPR_32RegClass;
}

// In order to fold immediates into copies, we need to change the
// copy to a MOV.
// In order to fold immediates into copies, we need to change the copy to a
// MOV. Find a compatible mov instruction with the value.
for (unsigned MovOp :
{AMDGPU::S_MOV_B32, AMDGPU::V_MOV_B32_e32, AMDGPU::S_MOV_B64,
AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64}) {
const MCInstrDesc &MovDesc = TII->get(MovOp);
assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);

const TargetRegisterClass *MovDstRC =
TRI->getRegClass(MovDesc.operands()[0].RegClass);

// Fold if the destination register class of the MOV instruction (ResRC)
// is a superclass of (or equal to) the destination register class of the
// COPY (DestRC). If this condition fails, folding would be illegal.
if (!DestRC->hasSuperClassEq(MovDstRC))
continue;

unsigned MovOp = TII->getMovOpcode(DestRC);
if (MovOp == AMDGPU::COPY)
return;
const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1;
const TargetRegisterClass *MovSrcRC =
TRI->getRegClass(MovDesc.operands()[SrcIdx].RegClass);

// Fold if the destination register class of the MOV instruction (ResRC)
// is a superclass of (or equal to) the destination register class of the
// COPY (DestRC). If this condition fails, folding would be illegal.
const MCInstrDesc &MovDesc = TII->get(MovOp);
assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
const TargetRegisterClass *ResRC =
TRI->getRegClass(MovDesc.operands()[0].RegClass);
if (!DestRC->hasSuperClassEq(ResRC))
return;
if (UseSubReg)
MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg);
if (!MRI->constrainRegClass(SrcReg, MovSrcRC))
break;

MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
while (ImpOpI != ImpOpE) {
MachineInstr::mop_iterator Tmp = ImpOpI;
ImpOpI++;
UseMI->removeOperand(UseMI->getOperandNo(Tmp));
}
UseMI->setDesc(TII->get(MovOp));

if (MovOp == AMDGPU::V_MOV_B16_t16_e64) {
const auto &SrcOp = UseMI->getOperand(UseOpIdx);
MachineOperand NewSrcOp(SrcOp);
MachineFunction *MF = UseMI->getParent()->getParent();
UseMI->removeOperand(1);
UseMI->addOperand(*MF, MachineOperand::CreateImm(0)); // src0_modifiers
UseMI->addOperand(NewSrcOp); // src0
UseMI->addOperand(*MF, MachineOperand::CreateImm(0)); // op_sel
UseOpIdx = 2;
UseOp = &UseMI->getOperand(UseOpIdx);
MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
while (ImpOpI != ImpOpE) {
MachineInstr::mop_iterator Tmp = ImpOpI;
ImpOpI++;
UseMI->removeOperand(UseMI->getOperandNo(Tmp));
}
Comment on lines +1308 to +1314
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@Pierre-vh Pierre-vh Aug 26, 2025

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Don't we have helpers to remove all implicit operands? It feels like we should have one
Maybe put this in a small static helper ?

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@arsenm arsenm Aug 26, 2025

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This is just re-indenting existing code, not touching this here

UseMI->setDesc(MovDesc);

if (MovOp == AMDGPU::V_MOV_B16_t16_e64) {
const auto &SrcOp = UseMI->getOperand(UseOpIdx);
MachineOperand NewSrcOp(SrcOp);
MachineFunction *MF = UseMI->getParent()->getParent();
UseMI->removeOperand(1);
UseMI->addOperand(*MF, MachineOperand::CreateImm(0)); // src0_modifiers
UseMI->addOperand(NewSrcOp); // src0
UseMI->addOperand(*MF, MachineOperand::CreateImm(0)); // op_sel
UseOpIdx = SrcIdx;
UseOp = &UseMI->getOperand(UseOpIdx);
}
CopiesToReplace.push_back(UseMI);
break;
}
CopiesToReplace.push_back(UseMI);

// We failed to replace the copy, so give up.
if (UseMI->getOpcode() == AMDGPU::COPY)
return;

} else {
if (UseMI->isCopy() && OpToFold.isReg() &&
UseMI->getOperand(0).getReg().isVirtual() &&
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,7 @@ define amdgpu_kernel void @br_cc_f16_imm_a(
; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v1.l
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB1_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0x3800
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
; GFX11-TRUE16-NEXT: .LBB1_2: ; %two
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
Expand Down Expand Up @@ -303,7 +303,7 @@ define amdgpu_kernel void @br_cc_f16_imm_b(
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v1.l
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB2_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %two
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0x3800
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
; GFX11-TRUE16-NEXT: .LBB2_2: ; %one
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
Expand Down
93 changes: 63 additions & 30 deletions llvm/test/CodeGen/AMDGPU/call-argument-types.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -426,16 +426,27 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: test_call_external_void_func_i8_imm:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i8@rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i8@rel32@hi+12
; GFX11-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-NEXT: s_mov_b32 s32, 0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_endpgm
; GFX11-TRUE16-LABEL: test_call_external_void_func_i8_imm:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
; GFX11-TRUE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-TRUE16-NEXT: s_add_u32 s2, s2, external_void_func_i8@rel32@lo+4
; GFX11-TRUE16-NEXT: s_addc_u32 s3, s3, external_void_func_i8@rel32@hi+12
; GFX11-TRUE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-TRUE16-NEXT: s_mov_b32 s32, 0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: test_call_external_void_func_i8_imm:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX11-FAKE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-FAKE16-NEXT: s_add_u32 s2, s2, external_void_func_i8@rel32@lo+4
; GFX11-FAKE16-NEXT: s_addc_u32 s3, s3, external_void_func_i8@rel32@hi+12
; GFX11-FAKE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-FAKE16-NEXT: s_mov_b32 s32, 0
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
;
; HSA-LABEL: test_call_external_void_func_i8_imm:
; HSA: ; %bb.0:
Expand Down Expand Up @@ -723,16 +734,27 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: test_call_external_void_func_i16_imm:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i16@rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i16@rel32@hi+12
; GFX11-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-NEXT: s_mov_b32 s32, 0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_endpgm
; GFX11-TRUE16-LABEL: test_call_external_void_func_i16_imm:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b
; GFX11-TRUE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-TRUE16-NEXT: s_add_u32 s2, s2, external_void_func_i16@rel32@lo+4
; GFX11-TRUE16-NEXT: s_addc_u32 s3, s3, external_void_func_i16@rel32@hi+12
; GFX11-TRUE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-TRUE16-NEXT: s_mov_b32 s32, 0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: test_call_external_void_func_i16_imm:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX11-FAKE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-FAKE16-NEXT: s_add_u32 s2, s2, external_void_func_i16@rel32@lo+4
; GFX11-FAKE16-NEXT: s_addc_u32 s3, s3, external_void_func_i16@rel32@hi+12
; GFX11-FAKE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-FAKE16-NEXT: s_mov_b32 s32, 0
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
;
; HSA-LABEL: test_call_external_void_func_i16_imm:
; HSA: ; %bb.0:
Expand Down Expand Up @@ -1642,16 +1664,27 @@ define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: s_endpgm
;
; GFX11-LABEL: test_call_external_void_func_f16_imm:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_mov_b32_e32 v0, 0x4400
; GFX11-NEXT: s_getpc_b64 s[2:3]
; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f16@rel32@lo+4
; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f16@rel32@hi+12
; GFX11-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-NEXT: s_mov_b32 s32, 0
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: s_endpgm
; GFX11-TRUE16-LABEL: test_call_external_void_func_f16_imm:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400
; GFX11-TRUE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-TRUE16-NEXT: s_add_u32 s2, s2, external_void_func_f16@rel32@lo+4
; GFX11-TRUE16-NEXT: s_addc_u32 s3, s3, external_void_func_f16@rel32@hi+12
; GFX11-TRUE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-TRUE16-NEXT: s_mov_b32 s32, 0
; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: test_call_external_void_func_f16_imm:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400
; GFX11-FAKE16-NEXT: s_getpc_b64 s[2:3]
; GFX11-FAKE16-NEXT: s_add_u32 s2, s2, external_void_func_f16@rel32@lo+4
; GFX11-FAKE16-NEXT: s_addc_u32 s3, s3, external_void_func_f16@rel32@hi+12
; GFX11-FAKE16-NEXT: s_mov_b64 s[6:7], s[0:1]
; GFX11-FAKE16-NEXT: s_mov_b32 s32, 0
; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
;
; HSA-LABEL: test_call_external_void_func_f16_imm:
; HSA: ; %bb.0:
Expand Down
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