AMDGPU: Correct inst size for av_mov_b32_imm_pseudo #154459
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In the AGPR case this will be an 8 byte instruction, which is part of why this case is a pain to deal with in the first place.
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesIn the AGPR case this will be an 8 byte instruction, Full diff: https://github.com/llvm/llvm-project/pull/154459.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index bd5dfa92a8e43..d3c15bd8f672a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -155,7 +155,8 @@ def AV_MOV_B32_IMM_PSEUDO
let VOP3 = 1;
let isMoveImm = 1;
let SchedRW = [Write32Bit];
- let Size = 4;
+ let Size = 8;
+ let FixedSize = true;
let UseNamedOperandTable = 1;
}
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shiltian
approved these changes
Aug 20, 2025
shiltian
reviewed
Aug 20, 2025
| let SchedRW = [Write32Bit]; | ||
| let Size = 4; | ||
| let Size = 8; | ||
| let FixedSize = true; |
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What if it is lowered to V_MOV_B32?
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It will be 4, but we need to report worst case
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Will it affect code size calculation?
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Yes, but by the time we do anything with the size calculation these should have been expanded already. I'm not sure anything is using getInstSizeInBytes this early
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In the AGPR case this will be an 8 byte instruction,
which is part of why this case is a pain to deal with in the
first place.