[RISCV] Add MC support for more P extension instructions. #153629
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This implements pages 10-14 from https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf Test cases copied from llvm#123271 with a couple mistakes fixed. Co-authored-by: realqhc <[email protected]>
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@llvm/pr-subscribers-mc @llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis implements pages 10-14 from Test cases copied from #123271 with a couple mistakes fixed. Patch is 41.49 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/153629.diff 5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index db3942b3ac7e7..468a4400f2294 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -149,6 +149,15 @@ class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>
let Inst{26-25} = w;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
+ : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
+ let Inst{31} = 0b1;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -292,3 +301,250 @@ let Predicates = [HasStdExtP, IsRV64] in {
def PSRA_WS : RVPBinaryScalar_rr<0b100, 0b01, 0b100, "psra.ws">;
} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def PADD_H : RVPBinary_rr<0b0000, 0b00, 0b000, "padd.h">;
+ def PADD_B : RVPBinary_rr<0b0000, 0b10, 0b000, "padd.b">;
+
+ def PSADD_H : RVPBinary_rr<0b0010, 0b00, 0b000, "psadd.h">;
+ def PSADD_B : RVPBinary_rr<0b0010, 0b10, 0b000, "psadd.b">;
+
+ def PAADD_H : RVPBinary_rr<0b0011, 0b00, 0b000, "paadd.h">;
+ def PAADD_B : RVPBinary_rr<0b0011, 0b10, 0b000, "paadd.b">;
+
+ def PSADDU_H : RVPBinary_rr<0b0110, 0b00, 0b000, "psaddu.h">;
+ def PSADDU_B : RVPBinary_rr<0b0110, 0b10, 0b000, "psaddu.b">;
+
+ def PAADDU_H : RVPBinary_rr<0b0111, 0b00, 0b000, "paaddu.h">;
+ def PAADDU_B : RVPBinary_rr<0b0111, 0b10, 0b000, "paaddu.b">;
+
+ def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">;
+ def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">;
+
+ def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">;
+ def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">;
+
+ def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">;
+ def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">;
+
+ def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">;
+ def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">;
+
+ def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">;
+ def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">;
+
+ def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">;
+ def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">;
+
+ def PASUBU_H : RVPBinary_rr<0b1111, 0b00, 0b000, "pasubu.h">;
+ def PASUBU_B : RVPBinary_rr<0b1111, 0b10, 0b000, "pasubu.b">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def SADD : RVPBinary_rr<0b0010, 0b01, 0b000, "sadd">;
+
+ def AADD : RVPBinary_rr<0b0011, 0b01, 0b000, "aadd">;
+
+ def SADDU : RVPBinary_rr<0b0110, 0b01, 0b000, "saddu">;
+
+ def AADDU : RVPBinary_rr<0b0111, 0b01, 0b000, "aaddu">;
+
+ def SSUB : RVPBinary_rr<0b1010, 0b01, 0b000, "ssub">;
+
+ def ASUB : RVPBinary_rr<0b1011, 0b01, 0b000, "asub">;
+
+ def SSUBU : RVPBinary_rr<0b1110, 0b01, 0b000, "ssubu">;
+
+ def ASUBU : RVPBinary_rr<0b1111, 0b01, 0b000, "asubu">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PADD_W : RVPBinary_rr<0b0000, 0b01, 0b000, "padd.w">;
+
+ def PSADD_W : RVPBinary_rr<0b0010, 0b01, 0b000, "psadd.w">;
+
+ def PAADD_W : RVPBinary_rr<0b0011, 0b01, 0b000, "paadd.w">;
+
+ def PSADDU_W : RVPBinary_rr<0b0110, 0b01, 0b000, "psaddu.w">;
+
+ def PAADDU_W : RVPBinary_rr<0b0111, 0b01, 0b000, "paaddu.w">;
+
+ def PSUB_W : RVPBinary_rr<0b1000, 0b01, 0b000, "psub.w">;
+
+ def PSSUB_W : RVPBinary_rr<0b1010, 0b01, 0b000, "pssub.w">;
+
+ def PASUB_W : RVPBinary_rr<0b1011, 0b01, 0b000, "pasub.w">;
+
+ def PSSUBU_W : RVPBinary_rr<0b1110, 0b01, 0b000, "pssubu.w">;
+
+ def PASUBU_W : RVPBinary_rr<0b1111, 0b01, 0b000, "pasubu.w">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def SLX : RVPBinary_rr<0b0001, 0b11, 0b001, "slx">;
+
+ def PMUL_H_B01 : RVPBinary_rr<0b0010, 0b00, 0b001, "pmul.h.b01">;
+
+ def MVM : RVPBinary_rr<0b0101, 0b00, 0b001, "mvm">;
+ def MVMN : RVPBinary_rr<0b0101, 0b01, 0b001, "mvmn">;
+ def MERGE : RVPBinary_rr<0b0101, 0b10, 0b001, "merge">;
+ def SRX : RVPBinary_rr<0b0101, 0b11, 0b001, "srx">;
+
+ def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">;
+ def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">;
+
+ def PDIFSUMAU_B : RVPBinary_rr<0b0111, 0b10, 0b001, "pdifsumau.b">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">;
+
+ def MACC_H01 : RVPBinary_rr<0b0011, 0b01, 0b001, "macc.h01">;
+
+ def MULU_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "mulu.h01">;
+
+ def MACCU_H01 : RVPBinary_rr<0b0111, 0b01, 0b001, "maccu.h01">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PMUL_W_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "pmul.w.h01">;
+ def MUL_W01 : RVPBinary_rr<0b0010, 0b11, 0b001, "mul.w01">;
+
+ def PMACC_W_H01 : RVPBinary_rr<0b0011, 0b01, 0b001, "pmacc.w.h01">;
+ def MACC_W01 : RVPBinary_rr<0b0011, 0b11, 0b001, "macc.w01">;
+
+ def PMULU_W_H01 : RVPBinary_rr<0b0110, 0b01, 0b001, "pmulu.w.h01">;
+ def MULU_W01 : RVPBinary_rr<0b0110, 0b11, 0b001, "mulu.w01">;
+
+ def PMACCU_W_H01 : RVPBinary_rr<0b0111, 0b01, 0b001, "pmaccu.w.h01">;
+ def MACCU_W01 : RVPBinary_rr<0b0111, 0b11, 0b001, "maccu.w01">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
+// Here we include the 0 in the f field to reduce number of tablegen classes.
+let Predicates = [HasStdExtP] in {
+ def PSH1ADD_H : RVPBinary_rr<0b0100, 0b00, 0b010, "psh1add.h">;
+
+ def PSSH1SADD_H : RVPBinary_rr<0b0110, 0b00, 0b010, "pssh1sadd.h">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def SSH1SADD : RVPBinary_rr<0b0110, 0b01, 0b010, "ssh1sadd">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PSH1ADD_W : RVPBinary_rr<0b0100, 0b01, 0b010, "psh1add.w">;
+
+ def PSSH1SADD_W : RVPBinary_rr<0b0110, 0b01, 0b010, "pssh1sadd.w">;
+
+ def UNZIP8P : RVPBinary_rr<0b1100, 0b00, 0b010, "unzip8p">;
+ def UNZIP16P : RVPBinary_rr<0b1100, 0b01, 0b010, "unzip16p">;
+ def UNZIP8HP : RVPBinary_rr<0b1100, 0b10, 0b010, "unzip8hp">;
+ def UNZIP16HP : RVPBinary_rr<0b1100, 0b11, 0b010, "unzip16hp">;
+
+ def ZIP8P : RVPBinary_rr<0b1110, 0b00, 0b010, "zip8p">;
+ def ZIP16P : RVPBinary_rr<0b1110, 0b01, 0b010, "zip16p">;
+ def ZIP8HP : RVPBinary_rr<0b1110, 0b10, 0b010, "zip8hp">;
+ def ZIP16HP : RVPBinary_rr<0b1110, 0b11, 0b010, "zip16hp">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+ def PMUL_H_B00 : RVPBinary_rr<0b0000, 0b00, 0b011, "pmul.h.b00">;
+
+ def PMUL_H_B11 : RVPBinary_rr<0b0010, 0b00, 0b011, "pmul.h.b11">;
+
+ def PMULU_H_B00 : RVPBinary_rr<0b0100, 0b00, 0b011, "pmulu.h.b00">;
+
+ def PMULU_H_B11 : RVPBinary_rr<0b0110, 0b00, 0b011, "pmulu.h.b11">;
+
+ def PMULSU_H_B00 : RVPBinary_rr<0b1100, 0b00, 0b011, "pmulsu.h.b00">;
+
+ def PMULSU_H_B11 : RVPBinary_rr<0b1110, 0b00, 0b011, "pmulsu.h.b11">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def MUL_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "mul.h00">;
+
+ def MACC_H00 : RVPBinary_rr<0b0001, 0b01, 0b011, "macc.h00">;
+
+ def MUL_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "mul.h11">;
+
+ def MACC_H11 : RVPBinary_rr<0b0011, 0b01, 0b011, "macc.h11">;
+
+ def MULU_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "mulu.h00">;
+
+ def MACCU_H00 : RVPBinary_rr<0b0101, 0b01, 0b011, "maccu.h00">;
+
+ def MULU_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "mulu.h11">;
+
+ def MACCU_H11 : RVPBinary_rr<0b0111, 0b01, 0b011, "maccu.h11">;
+
+ def MULSU_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "mulsu.h00">;
+
+ def MACCSU_H00 : RVPBinary_rr<0b1101, 0b01, 0b011, "maccsu.h00">;
+
+ def MULSU_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "mulsu.h11">;
+
+ def MACCSU_H11 : RVPBinary_rr<0b1111, 0b01, 0b011, "maccsu.h11">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PMUL_W_H00 : RVPBinary_rr<0b0000, 0b01, 0b011, "pmul.w.h00">;
+ def MUL_W00 : RVPBinary_rr<0b0000, 0b11, 0b011, "mul.w00">;
+
+ def PMACC_W_H00 : RVPBinary_rr<0b0001, 0b01, 0b011, "pmacc.w.h00">;
+ def MACC_W00 : RVPBinary_rr<0b0001, 0b11, 0b011, "macc.w00">;
+
+ def PMUL_W_H11 : RVPBinary_rr<0b0010, 0b01, 0b011, "pmul.w.h11">;
+ def MUL_W11 : RVPBinary_rr<0b0010, 0b11, 0b011, "mul.w11">;
+
+ def PMACC_W_H11 : RVPBinary_rr<0b0011, 0b01, 0b011, "pmacc.w.h11">;
+ def MACC_W11 : RVPBinary_rr<0b0011, 0b11, 0b011, "macc.w11">;
+
+ def PMULU_W_H00 : RVPBinary_rr<0b0100, 0b01, 0b011, "pmulu.w.h00">;
+ def MULU_W00 : RVPBinary_rr<0b0100, 0b11, 0b011, "mulu.w00">;
+
+ def PMACCU_W_H00 : RVPBinary_rr<0b0101, 0b01, 0b011, "pmaccu.w.h00">;
+ def MACCU_W00 : RVPBinary_rr<0b0101, 0b11, 0b011, "maccu.w00">;
+
+ def PMULU_W_H11 : RVPBinary_rr<0b0110, 0b01, 0b011, "pmulu.w.h11">;
+ def MULU_W11 : RVPBinary_rr<0b0110, 0b11, 0b011, "mulu.w11">;
+
+ def PMACCU_W_H11 : RVPBinary_rr<0b0111, 0b01, 0b011, "pmaccu.w.h11">;
+ def MACCU_W11 : RVPBinary_rr<0b0111, 0b11, 0b011, "maccu.w11">;
+
+ def PMULSU_W_H00 : RVPBinary_rr<0b1100, 0b01, 0b011, "pmulsu.w.h00">;
+ def MULSU_W00 : RVPBinary_rr<0b1100, 0b11, 0b011, "mulsu.w00">;
+
+ def PMACCSU_W_H00 : RVPBinary_rr<0b1101, 0b01, 0b011, "pmaccsu.w.h00">;
+ def MACCSU_W00 : RVPBinary_rr<0b1101, 0b11, 0b011, "maccsu.w00">;
+
+ def PMULSU_W_H11 : RVPBinary_rr<0b1110, 0b01, 0b011, "pmulsu.w.h11">;
+ def MULSU_W11 : RVPBinary_rr<0b1110, 0b11, 0b011, "mulsu.w11">;
+
+ def PMACCSU_W_H11 : RVPBinary_rr<0b1111, 0b01, 0b011, "pmaccsu.w.h11">;
+ def MACCSU_W11 : RVPBinary_rr<0b1111, 0b11, 0b011, "maccsu.w11">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+// Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27.
+// Here we include the 0 in the f field to reduce number of tablegen classes.
+let Predicates = [HasStdExtP] in {
+ def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">;
+
+ def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">;
+
+ def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">;
+
+ def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in {
+ def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">;
+
+ def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">;
+
+ def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">;
+} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only"
+let Predicates = [HasStdExtP, IsRV64] in {
+ def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">;
+
+ def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">;
+ def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">;
+
+ def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">;
+ def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">;
+
+ def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
+ def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
+} // Predicates = [HasStdExtP, IsRV64]
diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s
index ebd2d21b7fcf4..7dd73d077bf3a 100644
--- a/llvm/test/MC/RISCV/rv32p-invalid.s
+++ b/llvm/test/MC/RISCV/rv32p-invalid.s
@@ -45,3 +45,64 @@ psrl.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the follow
predsum.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
predsumu.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
psra.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+padd.w t3, s0, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psadd.w t3, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+paadd.w t5, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psaddu.w s0, s2, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+paaddu.w s0, t1, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+psub.w t3, a0, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssub.w t3, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pasub.w t3, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssubu.w a0, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pasubu.w a0, t3, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+pmul.w.h01 s2, t5, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w01 t5, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h01 t1, t1, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w01 s2, a0, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h01 t1, a4, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w01 t5, t1, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h01 t5, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w01 a0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+psh1add.w s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pssh1sadd.w a4, t3, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip8p a4, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip16p t5, a4, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip8hp s0, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+unzip16hp a0, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip8p t5, t3, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip16p a0, t5, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip8hp t5, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+zip16hp t1, t5, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+pmul.w.h00 s2, t1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w00 a4, a0, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h00 s2, t5, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w00 t1, a0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmul.w.h11 s0, a4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mul.w11 a0, t3, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmacc.w.h11 a4, a4, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+macc.w11 t3, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h00 a2, t3, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w00 a0, t5, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h00 t3, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w00 s2, t1, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulu.w.h11 s0, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulu.w11 s0, t1, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccu.w.h11 a0, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccu.w11 s2, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulsu.w.h00 t5, t5, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulsu.w00 t1, s0, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmulsu.w.h11 t1, t3, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+mulsu.w11 a2, s2, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccsu.w.h00 a4, a0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccsu.w00 a4, s2, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+pmaccsu.w.h11 a0, a2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+maccsu.w11 t5, a4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+
+ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
+ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s
index 3e65fef1524f4..0383e4ec1ea62 100644
--- a/llvm/test/MC/RISCV/rv32p-valid.s
+++ b/llvm/test/MC/RISCV/rv32p-valid.s
@@ -154,3 +154,222 @@ psra.hs ra, a1, a2
# CHECK-ASM-AND-OBJ: psra.bs sp, a2, a3
# CHECK-ASM: encoding: [0x1b,0x41,0xd6,0xcc]
psra.bs sp, a2, a3
+# CHECK-ASM-AND-OBJ: padd.h t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x80]
+padd.h t0, t1, t2
+# CHECK-ASM-AND-OBJ: padd.b ra, a1, a2
+# CHECK-ASM: encoding: [0xbb,0x80,0xc5,0x84]
+padd.b ra, a1, a2
+# CHECK-ASM-AND-OBJ: psadd.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0x91]
+psadd.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: sadd t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0x92]
+sadd t1, a7, a0
+# CHECK-ASM-AND-OBJ: psadd.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x94]
+psadd.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: paadd.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0x99]
+paadd.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: aadd t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0x9a]
+aadd t1, a7, a0
+# CHECK-ASM-AND-OBJ: paadd.b t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x9c]
+paadd.b t0, t1, t2
+# CHECK-ASM-AND-OBJ: psaddu.h t3, t4, t5
+# CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xb1]
+psaddu.h t3, t4, t5
+# CHECK-ASM-AND-OBJ: saddu t1, a7, a0
+# CHECK-ASM: encoding: [0x3b,0x83,0xa8,0xb2]
+saddu t1, a7, a0
+# CHECK-ASM-...
[truncated]
|
topperc
commented
Aug 14, 2025
| def MACCU_W01 : RVPBinary_rr<0b0111, 0b11, 0b001, "maccu.w01">; | ||
| } // Predicates = [HasStdExtP, IsRV64] | ||
|
|
||
| // Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27. |
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Note, I deviated slightly from how the spec is written here.
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This implements pages 10-14 from
https://jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
Test cases copied from #123271 with a couple mistakes fixed.