[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. #151706

link-xyq · 2025-08-01T14:38:38Z

The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features):

https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1

This patch only supports assembler.

github-actions · 2025-08-01T14:38:58Z

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llvmbot · 2025-08-01T14:39:29Z

@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-mc

@llvm/pr-subscribers-clang

Author: 林克 (link-xyq)

Changes

The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features):

https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1

This patch only supports assembler.

Full diff: https://github.com/llvm/llvm-project/pull/151706.diff

9 Files Affected:

(modified) clang/test/Driver/print-supported-extensions-riscv.c (+1)
(modified) llvm/docs/RISCVUsage.rst (+3)
(modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+14)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1)
(added) llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td (+141)
(modified) llvm/test/CodeGen/RISCV/features-info.ll (+1)
(added) llvm/test/MC/RISCV/rvv/xsmtvdot.s (+114)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 2503f2473d64a..1015ad3c0faa6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -192,6 +192,7 @@
 // CHECK-NEXT:     xsfvqmaccqoq         1.0       'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
 // CHECK-NEXT:     xsifivecdiscarddlone 1.0       'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
 // CHECK-NEXT:     xsifivecflushdlone   1.0       'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
+// CHECK-NEXT:     xsmtvdot             1.0       'XSMTVDot' (SpacemiT Vector Dot Product Extension)
 // CHECK-NEXT:     xtheadba             1.0       'XTHeadBa' (T-Head address calculation instructions)
 // CHECK-NEXT:     xtheadbb             1.0       'XTHeadBb' (T-Head basic bit-manipulation instructions)
 // CHECK-NEXT:     xtheadbs             1.0       'XTHeadBs' (T-Head single-bit instructions)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9f6ac558b6f7c..b6fab934abbf3 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -531,6 +531,9 @@ The current vendor extensions supported are:
 ``XAndesVDot``
   LLVM implements `version 5.0.0 of the Andes Vector Dot Product Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
 
+``XSMTVDot``
+  LLVM implements `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the specification.
+
 Experimental C Intrinsics
 =========================
 
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 67cc01e647a04..f1865ca8832ff 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -344,6 +344,17 @@ static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVREvenRegisterClass(MCInst &Inst, uint32_t RegNo,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
+  if (RegNo >= 32 || RegNo % 2)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::V0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
                                           uint64_t Address,
                                           const MCDisassembler *Decoder) {
@@ -672,6 +683,8 @@ static constexpr FeatureBitset XAndesGroup = {
     RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
     RISCV::FeatureVendorXAndesVDot};
 
+static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
+
 static constexpr DecoderListEntry DecoderList32[]{
     // Vendor Extensions
     {DecoderTableXVentana32,
@@ -689,6 +702,7 @@ static constexpr DecoderListEntry DecoderList32[]{
      {RISCV::FeatureVendorXMIPSCBOP},
      "MIPS mips.pref"},
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
+    {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     // Standard Extensions
     {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
     {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 171940e149815..a5285791a3b70 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1642,6 +1642,14 @@ def HasVendorXAndesVDot
       AssemblerPredicate<(all_of FeatureVendorXAndesVDot),
                          "'XAndesVDot' (Andes Vector Dot Product Extension)">;
 
+def FeatureVendorXSMTVDot
+    : RISCVExtension<1, 0, "SpacemiT Vector Dot Product Extension",
+                     [FeatureStdExtV]>;
+def HasVendorXSMTVDot
+    : Predicate<"Subtarget->hasVendorXSMTVDot()">,
+      AssemblerPredicate<(all_of FeatureVendorXSMTVDot),
+                         "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 653607827282e..06203d1a5b486 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2362,6 +2362,7 @@ include "RISCVInstrInfoXqccmp.td"
 include "RISCVInstrInfoXMips.td"
 include "RISCVInstrInfoXRivos.td"
 include "RISCVInstrInfoXAndes.td"
+include "RISCVInstrInfoXSMTVDot.td"
 
 //===----------------------------------------------------------------------===//
 // Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td
new file mode 100644
index 0000000000000..cccb8969da6f0
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td
@@ -0,0 +1,141 @@
+//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the xsmtvdot vendor extensions defined by SpacemiT.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+class SMTVDotOpcode<bits<7> val> {
+  bits<7> Value = val;
+}
+
+class SMTVEncoding2<bits<2> val> {
+  bits<2> Value = val;
+}
+
+def OPMMA       : SMTVDotOpcode<0b1110001>;
+def OPMMA_SLIDE : SMTVDotOpcode<0b1110011>;
+
+//===----------------------------------------------------------------------===//
+// Vector Dot-Product Sign Encoding
+// Defines the signed/unsigned mixing modes for vector dot-product operations.
+// Encoding format: [1:0] bits
+//   00: UU (Unsigned x Unsigned)
+//   01: US (Unsigned x Signed)
+//   10: SU (Signed x Unsigned)
+//   11: SS (Signed x Signed)
+//===----------------------------------------------------------------------===//
+def SMT_VDot_UU        : SMTVEncoding2<0b00>;
+def SMT_VDot_US        : SMTVEncoding2<0b01>;
+def SMT_VDot_SU        : SMTVEncoding2<0b10>;
+def SMT_VDot_SS        : SMTVEncoding2<0b11>;
+
+//===----------------------------------------------------------------------===//
+// Vector Dot-Product Sliding Window Modes
+// Encoding format: [1:0] bits
+//   00: Slide1 (1-element sliding stride)
+//   01: Slide2 (2-element sliding stride)
+//   10: Slide3 (3-element sliding stride)
+//   11: Reserved
+//
+// Used in sliding-window dot-product operations:
+//   vd = vs1 • vs2.slide{1|2|3}  // • = dot product
+//===----------------------------------------------------------------------===//
+def SMT_VDot_Slide1 : SMTVEncoding2<0b00>;
+def SMT_VDot_Slide2 : SMTVEncoding2<0b01>;
+def SMT_VDot_Slide3 : SMTVEncoding2<0b10>;
+
+//===----------------------------------------------------------------------===//
+// Instruction formats
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Base vector dot product (no slide) format.
+class RVInstVDot<bits<2> sign, string opcodestr, string argstr>
+    : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
+  bits<5> vd;
+  bits<5> vs1;
+  bits<5> vs2;
+
+  let Inst{31-25} = OPMMA.Value;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14} = 0b0;
+  let Inst{13-12} = sign;
+  let Inst{11-8} = vd{4-1};
+  let Inst{7} = 0b0;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+}
+
+// Sliding-window vector dot product format.
+class RVInstVDotSlide<bits<2>funct2, bits<2> sign, string opcodestr, string argstr>
+    : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
+  bits<5> vd;
+  bits<5> vs1;
+  bits<5> vs2;
+
+  let Inst{31-25} = OPMMA_SLIDE.Value;
+  let Inst{24-20} = vs2;
+  let Inst{19-16} = vs1{4-1};
+  let Inst{15-14} = funct2;
+  let Inst{13-12} = sign;
+  let Inst{11-8} = vd{4-1};
+  let Inst{7} = 0b0;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+}
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XSMT" in {
+
+let Predicates = [HasVendorXSMTVDot] in {
+// Base vector dot product (no slide) instructions
+// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30)
+//       due to hardware alignment constraints. Using odd registers may cause undefined behavior.
+// TODO: Enforce even-numbered vd.
+def VMADOT   : RVInstVDot<SMT_VDot_SS.Value{1-0}, "smt.vmadot",   "$vd, $vs1, $vs2">;
+def VMADOTU  : RVInstVDot<SMT_VDot_UU.Value{1-0}, "smt.vmadotu",  "$vd, $vs1, $vs2">;
+def VMADOTSU : RVInstVDot<SMT_VDot_SU.Value{1-0}, "smt.vmadotsu", "$vd, $vs1, $vs2">;
+def VMADOTUU : RVInstVDot<SMT_VDot_US.Value{1-0}, "smt.vmadotus", "$vd, $vs1, $vs2">;
+
+//===----------------------------------------------------------------------===//
+// Sliding-window Vector Dot Product Instructions
+//
+// The numeric suffix (1, 2, 3) specifies the stride of the sliding window:
+//   1: Window slides by 1 element per operation
+//   2: Window slides by 2 elements per operation
+//   3: Window slides by 3 elements per operation
+//
+// These instructions compute dot products with overlapping operand windows
+// where the window position increments by <N> elements between computations.
+//===----------------------------------------------------------------------===//
+// NOTE: Destination registers (vd) and first source register (vs1) MUST be
+//       even-numbered (v0, v2, ..., v30) due to hardware alignment constraints.
+//       Using odd registers may cause undefined behavior.
+// TODO: Enforce even-numbered vd.
+def VMADOT1   : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot1",   "$vd, $vs1, $vs2">;
+def VMADOT1U  : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot1u",  "$vd, $vs1, $vs2">;
+def VMADOT1SU : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot1su", "$vd, $vs1, $vs2">;
+def VMADOT1UU : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot1us", "$vd, $vs1, $vs2">;
+def VMADOT2   : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot2",   "$vd, $vs1, $vs2">;
+def VMADOT2U  : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot2u",  "$vd, $vs1, $vs2">;
+def VMADOT2SU : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot2su", "$vd, $vs1, $vs2">;
+def VMADOT2UU : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot2us", "$vd, $vs1, $vs2">;
+def VMADOT3   : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot3",   "$vd, $vs1, $vs2">;
+def VMADOT3U  : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot3u",  "$vd, $vs1, $vs2">;
+def VMADOT3SU : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot3su", "$vd, $vs1, $vs2">;
+def VMADOT3UU : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot3us", "$vd, $vs1, $vs2">;
+}
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index b94665b718ae7..cb7f892884e42 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -207,6 +207,7 @@
 ; CHECK-NEXT:   xsfvqmaccqoq                     - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)).
 ; CHECK-NEXT:   xsifivecdiscarddlone             - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction).
 ; CHECK-NEXT:   xsifivecflushdlone               - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction).
+; CHECK-NEXT:   xsmtvdot                         - 'XSMTVDot' (SpacemiT Vector Dot Product Extension).
 ; CHECK-NEXT:   xtheadba                         - 'XTHeadBa' (T-Head address calculation instructions).
 ; CHECK-NEXT:   xtheadbb                         - 'XTHeadBb' (T-Head basic bit-manipulation instructions).
 ; CHECK-NEXT:   xtheadbs                         - 'XTHeadBs' (T-Head single-bit instructions).
diff --git a/llvm/test/MC/RISCV/rvv/xsmtvdot.s b/llvm/test/MC/RISCV/rvv/xsmtvdot.s
new file mode 100644
index 0000000000000..b1f943b9170be
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/xsmtvdot.s
@@ -0,0 +1,114 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+xsmtvdot %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsmtvdot %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d  --mattr=+xsmtvdot --no-print-imm-hex - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d  --mattr=+xsmtvdot --no-print-imm-hex - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: smt.vmadot  v16, v0, v8
+# CHECK-ENCODING: [0x2b,0x38,0x80,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e280382b <unknown>
+smt.vmadot   v16, v0, v8
+
+# CHECK-INST: smt.vmadotu v18, v1, v9
+# CHECK-ENCODING: [0x2b,0x89,0x90,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e290892b <unknown>
+smt.vmadotu  v18, v1, v9
+
+# CHECK-INST: smt.vmadotsu        v20, v2, v10
+# CHECK-ENCODING: [0x2b,0x2a,0xa1,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e2a12a2b <unknown>
+smt.vmadotsu v20, v2, v10
+
+# CHECK-INST: smt.vmadotus        v22, v3, v11
+# CHECK-ENCODING: [0x2b,0x9b,0xb1,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e2b19b2b <unknown>
+smt.vmadotus v22, v3, v11
+
+# CHECK-INST: smt.vmadot1 v24, v16, v12
+# CHECK-ENCODING: [0x2b,0x3c,0xc8,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6c83c2b <unknown>
+smt.vmadot1   v24, v16, v12
+
+# CHECK-INST: smt.vmadot1u        v26, v18, v13
+# CHECK-ENCODING: [0x2b,0x0d,0xd9,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6d90d2b <unknown>
+smt.vmadot1u  v26, v18, v13
+
+# CHECK-INST: smt.vmadot1su       v28, v20, v14
+# CHECK-ENCODING: [0x2b,0x2e,0xea,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6ea2e2b <unknown>
+smt.vmadot1su v28, v20, v14
+
+# CHECK-INST: smt.vmadot1us       v30, v22, v15
+# CHECK-ENCODING: [0x2b,0x1f,0xfb,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6fb1f2b <unknown>
+smt.vmadot1us v30, v22, v15
+
+# CHECK-INST: smt.vmadot2 v0, v24, v4
+# CHECK-ENCODING: [0x2b,0x70,0x4c,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e64c702b <unknown>
+smt.vmadot2   v0, v24, v4
+
+# CHECK-INST: smt.vmadot2u        v2, v26, v5
+# CHECK-ENCODING: [0x2b,0x41,0x5d,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e65d412b <unknown>
+smt.vmadot2u  v2, v26, v5
+
+# CHECK-INST: smt.vmadot2su       v4, v28, v6
+# CHECK-ENCODING: [0x2b,0x62,0x6e,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e66e622b <unknown>
+smt.vmadot2su v4, v28, v6
+
+# CHECK-INST: smt.vmadot2us       v6, v30, v7
+# CHECK-ENCODING: [0x2b,0x53,0x7f,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e67f532b <unknown>
+smt.vmadot2us v6, v30, v7
+
+# CHECK-INST: smt.vmadot3 v8, v0, v8
+# CHECK-ENCODING: [0x2b,0xb4,0x80,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e680b42b <unknown>
+smt.vmadot3   v8, v0, v8
+
+# CHECK-INST: smt.vmadot3u        v10, v2, v9
+# CHECK-ENCODING: [0x2b,0x85,0x91,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e691852b <unknown>
+smt.vmadot3u  v10, v2, v9
+
+# CHECK-INST: smt.vmadot3su       v12, v4, v10
+# CHECK-ENCODING: [0x2b,0xa6,0xa2,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6a2a62b <unknown>
+smt.vmadot3su v12, v4, v10
+
+# CHECK-INST: smt.vmadot3us       v14, v6, v11
+# CHECK-ENCODING: [0x2b,0x97,0xb3,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6b3972b <unknown>
+smt.vmadot3us v14, v6, v11
\ No newline at end of file
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 319538eaea135..8d828d346832e 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1163,6 +1163,7 @@ R"(All available -march extensions for RISC-V
     xsfvqmaccqoq         1.0
     xsifivecdiscarddlone 1.0
     xsifivecflushdlone   1.0
+    xsmtvdot             1.0
     xtheadba             1.0
     xtheadbb             1.0
     xtheadbs             1.0

llvmbot · 2025-08-01T14:39:29Z

@llvm/pr-subscribers-clang-driver

Author: 林克 (link-xyq)

Changes

The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features):

https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1

This patch only supports assembler.

Full diff: https://github.com/llvm/llvm-project/pull/151706.diff

9 Files Affected:

(modified) clang/test/Driver/print-supported-extensions-riscv.c (+1)
(modified) llvm/docs/RISCVUsage.rst (+3)
(modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+14)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8)
(modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1)
(added) llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td (+141)
(modified) llvm/test/CodeGen/RISCV/features-info.ll (+1)
(added) llvm/test/MC/RISCV/rvv/xsmtvdot.s (+114)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 2503f2473d64a..1015ad3c0faa6 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -192,6 +192,7 @@
 // CHECK-NEXT:     xsfvqmaccqoq         1.0       'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
 // CHECK-NEXT:     xsifivecdiscarddlone 1.0       'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
 // CHECK-NEXT:     xsifivecflushdlone   1.0       'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
+// CHECK-NEXT:     xsmtvdot             1.0       'XSMTVDot' (SpacemiT Vector Dot Product Extension)
 // CHECK-NEXT:     xtheadba             1.0       'XTHeadBa' (T-Head address calculation instructions)
 // CHECK-NEXT:     xtheadbb             1.0       'XTHeadBb' (T-Head basic bit-manipulation instructions)
 // CHECK-NEXT:     xtheadbs             1.0       'XTHeadBs' (T-Head single-bit instructions)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9f6ac558b6f7c..b6fab934abbf3 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -531,6 +531,9 @@ The current vendor extensions supported are:
 ``XAndesVDot``
   LLVM implements `version 5.0.0 of the Andes Vector Dot Product Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
 
+``XSMTVDot``
+  LLVM implements `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the specification.
+
 Experimental C Intrinsics
 =========================
 
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 67cc01e647a04..f1865ca8832ff 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -344,6 +344,17 @@ static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeVREvenRegisterClass(MCInst &Inst, uint32_t RegNo,
+                                              uint64_t Address,
+                                              const MCDisassembler *Decoder) {
+  if (RegNo >= 32 || RegNo % 2)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::V0 + RegNo;
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
                                           uint64_t Address,
                                           const MCDisassembler *Decoder) {
@@ -672,6 +683,8 @@ static constexpr FeatureBitset XAndesGroup = {
     RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
     RISCV::FeatureVendorXAndesVDot};
 
+static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
+
 static constexpr DecoderListEntry DecoderList32[]{
     // Vendor Extensions
     {DecoderTableXVentana32,
@@ -689,6 +702,7 @@ static constexpr DecoderListEntry DecoderList32[]{
      {RISCV::FeatureVendorXMIPSCBOP},
      "MIPS mips.pref"},
     {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
+    {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
     // Standard Extensions
     {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
     {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 171940e149815..a5285791a3b70 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1642,6 +1642,14 @@ def HasVendorXAndesVDot
       AssemblerPredicate<(all_of FeatureVendorXAndesVDot),
                          "'XAndesVDot' (Andes Vector Dot Product Extension)">;
 
+def FeatureVendorXSMTVDot
+    : RISCVExtension<1, 0, "SpacemiT Vector Dot Product Extension",
+                     [FeatureStdExtV]>;
+def HasVendorXSMTVDot
+    : Predicate<"Subtarget->hasVendorXSMTVDot()">,
+      AssemblerPredicate<(all_of FeatureVendorXSMTVDot),
+                         "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 653607827282e..06203d1a5b486 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2362,6 +2362,7 @@ include "RISCVInstrInfoXqccmp.td"
 include "RISCVInstrInfoXMips.td"
 include "RISCVInstrInfoXRivos.td"
 include "RISCVInstrInfoXAndes.td"
+include "RISCVInstrInfoXSMTVDot.td"
 
 //===----------------------------------------------------------------------===//
 // Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td
new file mode 100644
index 0000000000000..cccb8969da6f0
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td
@@ -0,0 +1,141 @@
+//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the xsmtvdot vendor extensions defined by SpacemiT.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+class SMTVDotOpcode<bits<7> val> {
+  bits<7> Value = val;
+}
+
+class SMTVEncoding2<bits<2> val> {
+  bits<2> Value = val;
+}
+
+def OPMMA       : SMTVDotOpcode<0b1110001>;
+def OPMMA_SLIDE : SMTVDotOpcode<0b1110011>;
+
+//===----------------------------------------------------------------------===//
+// Vector Dot-Product Sign Encoding
+// Defines the signed/unsigned mixing modes for vector dot-product operations.
+// Encoding format: [1:0] bits
+//   00: UU (Unsigned x Unsigned)
+//   01: US (Unsigned x Signed)
+//   10: SU (Signed x Unsigned)
+//   11: SS (Signed x Signed)
+//===----------------------------------------------------------------------===//
+def SMT_VDot_UU        : SMTVEncoding2<0b00>;
+def SMT_VDot_US        : SMTVEncoding2<0b01>;
+def SMT_VDot_SU        : SMTVEncoding2<0b10>;
+def SMT_VDot_SS        : SMTVEncoding2<0b11>;
+
+//===----------------------------------------------------------------------===//
+// Vector Dot-Product Sliding Window Modes
+// Encoding format: [1:0] bits
+//   00: Slide1 (1-element sliding stride)
+//   01: Slide2 (2-element sliding stride)
+//   10: Slide3 (3-element sliding stride)
+//   11: Reserved
+//
+// Used in sliding-window dot-product operations:
+//   vd = vs1 • vs2.slide{1|2|3}  // • = dot product
+//===----------------------------------------------------------------------===//
+def SMT_VDot_Slide1 : SMTVEncoding2<0b00>;
+def SMT_VDot_Slide2 : SMTVEncoding2<0b01>;
+def SMT_VDot_Slide3 : SMTVEncoding2<0b10>;
+
+//===----------------------------------------------------------------------===//
+// Instruction formats
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Base vector dot product (no slide) format.
+class RVInstVDot<bits<2> sign, string opcodestr, string argstr>
+    : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
+  bits<5> vd;
+  bits<5> vs1;
+  bits<5> vs2;
+
+  let Inst{31-25} = OPMMA.Value;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = vs1;
+  let Inst{14} = 0b0;
+  let Inst{13-12} = sign;
+  let Inst{11-8} = vd{4-1};
+  let Inst{7} = 0b0;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+}
+
+// Sliding-window vector dot product format.
+class RVInstVDotSlide<bits<2>funct2, bits<2> sign, string opcodestr, string argstr>
+    : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
+  bits<5> vd;
+  bits<5> vs1;
+  bits<5> vs2;
+
+  let Inst{31-25} = OPMMA_SLIDE.Value;
+  let Inst{24-20} = vs2;
+  let Inst{19-16} = vs1{4-1};
+  let Inst{15-14} = funct2;
+  let Inst{13-12} = sign;
+  let Inst{11-8} = vd{4-1};
+  let Inst{7} = 0b0;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+}
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XSMT" in {
+
+let Predicates = [HasVendorXSMTVDot] in {
+// Base vector dot product (no slide) instructions
+// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30)
+//       due to hardware alignment constraints. Using odd registers may cause undefined behavior.
+// TODO: Enforce even-numbered vd.
+def VMADOT   : RVInstVDot<SMT_VDot_SS.Value{1-0}, "smt.vmadot",   "$vd, $vs1, $vs2">;
+def VMADOTU  : RVInstVDot<SMT_VDot_UU.Value{1-0}, "smt.vmadotu",  "$vd, $vs1, $vs2">;
+def VMADOTSU : RVInstVDot<SMT_VDot_SU.Value{1-0}, "smt.vmadotsu", "$vd, $vs1, $vs2">;
+def VMADOTUU : RVInstVDot<SMT_VDot_US.Value{1-0}, "smt.vmadotus", "$vd, $vs1, $vs2">;
+
+//===----------------------------------------------------------------------===//
+// Sliding-window Vector Dot Product Instructions
+//
+// The numeric suffix (1, 2, 3) specifies the stride of the sliding window:
+//   1: Window slides by 1 element per operation
+//   2: Window slides by 2 elements per operation
+//   3: Window slides by 3 elements per operation
+//
+// These instructions compute dot products with overlapping operand windows
+// where the window position increments by <N> elements between computations.
+//===----------------------------------------------------------------------===//
+// NOTE: Destination registers (vd) and first source register (vs1) MUST be
+//       even-numbered (v0, v2, ..., v30) due to hardware alignment constraints.
+//       Using odd registers may cause undefined behavior.
+// TODO: Enforce even-numbered vd.
+def VMADOT1   : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot1",   "$vd, $vs1, $vs2">;
+def VMADOT1U  : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot1u",  "$vd, $vs1, $vs2">;
+def VMADOT1SU : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot1su", "$vd, $vs1, $vs2">;
+def VMADOT1UU : RVInstVDotSlide<SMT_VDot_Slide1.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot1us", "$vd, $vs1, $vs2">;
+def VMADOT2   : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot2",   "$vd, $vs1, $vs2">;
+def VMADOT2U  : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot2u",  "$vd, $vs1, $vs2">;
+def VMADOT2SU : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot2su", "$vd, $vs1, $vs2">;
+def VMADOT2UU : RVInstVDotSlide<SMT_VDot_Slide2.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot2us", "$vd, $vs1, $vs2">;
+def VMADOT3   : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_SS.Value{1-0}, "smt.vmadot3",   "$vd, $vs1, $vs2">;
+def VMADOT3U  : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_UU.Value{1-0}, "smt.vmadot3u",  "$vd, $vs1, $vs2">;
+def VMADOT3SU : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_SU.Value{1-0}, "smt.vmadot3su", "$vd, $vs1, $vs2">;
+def VMADOT3UU : RVInstVDotSlide<SMT_VDot_Slide3.Value, SMT_VDot_US.Value{1-0}, "smt.vmadot3us", "$vd, $vs1, $vs2">;
+}
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index b94665b718ae7..cb7f892884e42 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -207,6 +207,7 @@
 ; CHECK-NEXT:   xsfvqmaccqoq                     - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)).
 ; CHECK-NEXT:   xsifivecdiscarddlone             - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction).
 ; CHECK-NEXT:   xsifivecflushdlone               - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction).
+; CHECK-NEXT:   xsmtvdot                         - 'XSMTVDot' (SpacemiT Vector Dot Product Extension).
 ; CHECK-NEXT:   xtheadba                         - 'XTHeadBa' (T-Head address calculation instructions).
 ; CHECK-NEXT:   xtheadbb                         - 'XTHeadBb' (T-Head basic bit-manipulation instructions).
 ; CHECK-NEXT:   xtheadbs                         - 'XTHeadBs' (T-Head single-bit instructions).
diff --git a/llvm/test/MC/RISCV/rvv/xsmtvdot.s b/llvm/test/MC/RISCV/rvv/xsmtvdot.s
new file mode 100644
index 0000000000000..b1f943b9170be
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/xsmtvdot.s
@@ -0,0 +1,114 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+xsmtvdot %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsmtvdot %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d  --mattr=+xsmtvdot --no-print-imm-hex - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d  --mattr=+xsmtvdot --no-print-imm-hex - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: smt.vmadot  v16, v0, v8
+# CHECK-ENCODING: [0x2b,0x38,0x80,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e280382b <unknown>
+smt.vmadot   v16, v0, v8
+
+# CHECK-INST: smt.vmadotu v18, v1, v9
+# CHECK-ENCODING: [0x2b,0x89,0x90,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e290892b <unknown>
+smt.vmadotu  v18, v1, v9
+
+# CHECK-INST: smt.vmadotsu        v20, v2, v10
+# CHECK-ENCODING: [0x2b,0x2a,0xa1,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e2a12a2b <unknown>
+smt.vmadotsu v20, v2, v10
+
+# CHECK-INST: smt.vmadotus        v22, v3, v11
+# CHECK-ENCODING: [0x2b,0x9b,0xb1,0xe2]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e2b19b2b <unknown>
+smt.vmadotus v22, v3, v11
+
+# CHECK-INST: smt.vmadot1 v24, v16, v12
+# CHECK-ENCODING: [0x2b,0x3c,0xc8,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6c83c2b <unknown>
+smt.vmadot1   v24, v16, v12
+
+# CHECK-INST: smt.vmadot1u        v26, v18, v13
+# CHECK-ENCODING: [0x2b,0x0d,0xd9,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6d90d2b <unknown>
+smt.vmadot1u  v26, v18, v13
+
+# CHECK-INST: smt.vmadot1su       v28, v20, v14
+# CHECK-ENCODING: [0x2b,0x2e,0xea,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6ea2e2b <unknown>
+smt.vmadot1su v28, v20, v14
+
+# CHECK-INST: smt.vmadot1us       v30, v22, v15
+# CHECK-ENCODING: [0x2b,0x1f,0xfb,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6fb1f2b <unknown>
+smt.vmadot1us v30, v22, v15
+
+# CHECK-INST: smt.vmadot2 v0, v24, v4
+# CHECK-ENCODING: [0x2b,0x70,0x4c,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e64c702b <unknown>
+smt.vmadot2   v0, v24, v4
+
+# CHECK-INST: smt.vmadot2u        v2, v26, v5
+# CHECK-ENCODING: [0x2b,0x41,0x5d,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e65d412b <unknown>
+smt.vmadot2u  v2, v26, v5
+
+# CHECK-INST: smt.vmadot2su       v4, v28, v6
+# CHECK-ENCODING: [0x2b,0x62,0x6e,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e66e622b <unknown>
+smt.vmadot2su v4, v28, v6
+
+# CHECK-INST: smt.vmadot2us       v6, v30, v7
+# CHECK-ENCODING: [0x2b,0x53,0x7f,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e67f532b <unknown>
+smt.vmadot2us v6, v30, v7
+
+# CHECK-INST: smt.vmadot3 v8, v0, v8
+# CHECK-ENCODING: [0x2b,0xb4,0x80,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e680b42b <unknown>
+smt.vmadot3   v8, v0, v8
+
+# CHECK-INST: smt.vmadot3u        v10, v2, v9
+# CHECK-ENCODING: [0x2b,0x85,0x91,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e691852b <unknown>
+smt.vmadot3u  v10, v2, v9
+
+# CHECK-INST: smt.vmadot3su       v12, v4, v10
+# CHECK-ENCODING: [0x2b,0xa6,0xa2,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6a2a62b <unknown>
+smt.vmadot3su v12, v4, v10
+
+# CHECK-INST: smt.vmadot3us       v14, v6, v11
+# CHECK-ENCODING: [0x2b,0x97,0xb3,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6b3972b <unknown>
+smt.vmadot3us v14, v6, v11
\ No newline at end of file
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 319538eaea135..8d828d346832e 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1163,6 +1163,7 @@ R"(All available -march extensions for RISC-V
     xsfvqmaccqoq         1.0
     xsifivecdiscarddlone 1.0
     xsifivecflushdlone   1.0
+    xsmtvdot             1.0
     xtheadba             1.0
     xtheadbb             1.0
     xtheadbs             1.0

link-xyq · 2025-08-01T15:00:49Z

For detailed instruction definitions and programming model specifications, please refer to:
https://github.com/space-mit/riscv-ime-extension-spec/releases/tag/v0429

Note:
The spacemit-x60 processor currently supports the following subset of this extension:

Integer dot-product matrix multiply-accumulate (int8 type)
Integer sliding-window dot-product matrix multiply-accumulate (int8 type)

llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td

llvm/docs/RISCVUsage.rst

llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td

llvm/lib/Target/RISCV/RISCVFeatures.td

llvm/test/MC/RISCV/rvv/xsmtvdot.s

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td

llvm/lib/Target/RISCV/RISCVInstrInfo.td

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir

[Fix] code review. Co-authored-by: Pengcheng Wang <[email protected]>

zqb-all · 2025-08-18T09:59:30Z

LGTM

github-actions · 2025-08-18T10:03:36Z

@link-xyq Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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jrtc27 · 2025-08-18T17:40:28Z

llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td

+def VMADOT3SU : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_SU, "smt.vmadot3su", "$vd, $vs1, $vs2">;
+def VMADOT3US : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_US, "smt.vmadot3us", "$vd, $vs1, $vs2">;
+}
+}


Please fix these files without newlines.

This has been addressed in #154457. PTAL: #154457

jrtc27 · 2025-08-18T17:40:41Z

llvm/test/MC/RISCV/xsmtvdot-invalid.s

+smt.vmadot3   v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+smt.vmadot3u  v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+smt.vmadot3su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+smt.vmadot3us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction


This has been addressed in #154457.

jrtc27 · 2025-08-18T17:40:49Z

llvm/test/MC/RISCV/xsmtvdot-valid.s

+# CHECK-ENCODING: [0x2b,0x97,0xb3,0xe6]
+# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}}
+# CHECK-UNKNOWN: e6b3972b <unknown>
+smt.vmadot3us v14, v6, v11


This has been addressed in #154457.

Add trailing newlines to the following files to comply with POSIX standards: - llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td - llvm/test/MC/RISCV/xsmtvdot-invalid.s - llvm/test/MC/RISCV/xsmtvdot-valid.s Closes llvm#151706

Add trailing newlines to the following files to comply with POSIX standards: - llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td - llvm/test/MC/RISCV/xsmtvdot-invalid.s - llvm/test/MC/RISCV/xsmtvdot-valid.s Closes #151706

llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' llvm:mc Machine (object) code labels Aug 1, 2025

zqb-all requested review from asb, lenary and zqb-all August 1, 2025 14:47

link-xyq force-pushed the 250801_riscv_spacemit_xsmtvdot branch from 67f8618 to 38ba3ca Compare August 1, 2025 14:54

link-xyq force-pushed the 250801_riscv_spacemit_xsmtvdot branch from 38ba3ca to 2445c6b Compare August 1, 2025 15:54

topperc reviewed Aug 1, 2025

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link-xyq force-pushed the 250801_riscv_spacemit_xsmtvdot branch 3 times, most recently from dbdecd3 to 5d3556f Compare August 7, 2025 07:27

link-xyq requested review from mshockwave, tclin914 and topperc August 7, 2025 08:11

mshockwave reviewed Aug 8, 2025

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link-xyq force-pushed the 250801_riscv_spacemit_xsmtvdot branch from 5d3556f to d31eb1c Compare August 12, 2025 01:03

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link-xyq and others added 15 commits August 18, 2025 17:15

[Fix] code review.

0c7a92a

[Refactor] Replace explicit .Value with type-safe SMTVEncoding2 param.

b9e6ec8

[RISCV] Enforce even-numbered vd for xsmtvdot.

3d857ca

[Fix] code review.

ff62a78

[Fix] code review.

11a2cd6

[Fix] code review.

a911e84

[Fix] Avoid change the register pressure.

0700683

[Fix] Avoid changing the VL operand on these instructions.

89f0e88

Update llvm/lib/Target/RISCV/RISCVRegisterInfo.td

3e91875

[Fix] code review. Co-authored-by: Pengcheng Wang <[email protected]>

[Fix] code review.

0578b4d

[Fix] code review.

a6ef5c1

[Fix] code review.

a436834

[Fix] code review.

2f82a7e

[Fix] code review.

89152e5

[Fix] code review.

4d6a898

link-xyq force-pushed the 250801_riscv_spacemit_xsmtvdot branch from 672f38a to 4d6a898 Compare August 18, 2025 09:16

zqb-all merged commit 6842cc5 into llvm:main Aug 18, 2025
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jrtc27 reviewed Aug 18, 2025

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link-xyq mentioned this pull request Aug 20, 2025

[RISCV][NFC] Ensure files end with newline. #154457

Merged

cbalint13 mentioned this pull request Aug 21, 2025

Added RISC-V V extension intrinsics for LLVM apache/tvm#18182

Open

alex-spacemit mentioned this pull request Oct 11, 2025

add xsmt ime2 extension nihui/ruapu#164

Merged

[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. #151706

[RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. #151706

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