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[RISCV] Add RISCVISD::LD_RV32/SD_RV32 to isWorthFoldingAdd. #151606

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Merged
merged 2 commits into from
Aug 1, 2025
Merged

[RISCV] Add RISCVISD::LD_RV32/SD_RV32 to isWorthFoldingAdd. #151606

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647f3d5
Pre-commit tests.
topperc Jul 31, 2025
27a6ad0
[RISCV] Add RISCVISD::LD_RV32/SD_RV32 to isWorthFoldingAdd.
topperc Jul 31, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2827,6 +2827,8 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
static bool isWorthFoldingAdd(SDValue Add) {
for (auto *User : Add->users()) {
if (User->getOpcode() != ISD::LOAD && User->getOpcode() != ISD::STORE &&
User->getOpcode() != RISCVISD::LD_RV32 &&
User->getOpcode() != RISCVISD::SD_RV32 &&
User->getOpcode() != ISD::ATOMIC_LOAD &&
User->getOpcode() != ISD::ATOMIC_STORE)
return false;
Expand All @@ -2841,6 +2843,9 @@ static bool isWorthFoldingAdd(SDValue Add) {
if (User->getOpcode() == ISD::ATOMIC_STORE &&
cast<AtomicSDNode>(User)->getVal() == Add)
return false;
if (User->getOpcode() == RISCVISD::SD_RV32 &&
(User->getOperand(0) == Add || User->getOperand(1) == Add))
return false;
if (isStrongerThanMonotonic(cast<MemSDNode>(User)->getSuccessOrdering()))
return false;
}
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19 changes: 19 additions & 0 deletions llvm/test/CodeGen/RISCV/zilsd.ll
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Expand Up @@ -117,3 +117,22 @@ entyr:
store i64 0, ptr @g
ret void
}

define void @large_offset(ptr nocapture %p, i64 %d) nounwind {
; CHECK-LABEL: large_offset:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a1, 4
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: ld a2, -384(a0)
; CHECK-NEXT: addi a2, a2, 1
; CHECK-NEXT: seqz a1, a2
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: sd a2, -384(a0)
; CHECK-NEXT: ret
entry:
%add.ptr = getelementptr inbounds i64, ptr %p, i64 2000
%a = load i64, ptr %add.ptr, align 8
%b = add i64 %a, 1
store i64 %b, ptr %add.ptr, align 8
ret void
}