Skip to content

[RISCV] Pass sign-extended value to isInt check in expandMul #150211

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jul 25, 2025
Merged

[RISCV] Pass sign-extended value to isInt check in expandMul #150211

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
a5a125c
[RISCV] Pass sign-extended value to isInt check in expandMul
svs-quic Jul 23, 2025
f648020
Pre-commit test
svs-quic Jul 24, 2025
4b685d3
Fix again
svs-quic Jul 24, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmt = CNode->getZExtValue();

// Don't do this if the Xqciac extension is enabled and the MulAmt in simm12.
if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt))
if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue()))
return SDValue();

const bool HasShlAdd = Subtarget.hasStdExtZba() ||
Expand Down
27 changes: 27 additions & 0 deletions llvm/test/CodeGen/RISCV/xqciac.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -463,3 +463,30 @@ entry:
%add = add nsw i32 %shlc1, %shlc2
ret i32 %add
}

define i32 @testmuliaddnegimm(i32 %a) {
; RV32IM-LABEL: testmuliaddnegimm:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 1
; RV32IM-NEXT: add a0, a1, a0
; RV32IM-NEXT: li a1, 3
; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IMXQCIAC: # %bb.0:
; RV32IMXQCIAC-NEXT: li a1, 3
; RV32IMXQCIAC-NEXT: qc.muliadd a1, a0, -3
; RV32IMXQCIAC-NEXT: mv a0, a1
; RV32IMXQCIAC-NEXT: ret
;
; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm:
; RV32IZBAMXQCIAC: # %bb.0:
; RV32IZBAMXQCIAC-NEXT: li a1, 3
; RV32IZBAMXQCIAC-NEXT: qc.muliadd a1, a0, -3
; RV32IZBAMXQCIAC-NEXT: mv a0, a1
; RV32IZBAMXQCIAC-NEXT: ret
%mul = mul i32 %a, -3
%add = add i32 %mul, 3
ret i32 %add
}