[RISCV] Correct alignment of one-active (de)interleave cases #150052
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Noticed this while going to rewrite the load case as a DAG combine. I don't have a test case which demonstrates this leading to a miscompile, but it seems like it could be possible.
Member
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@llvm/pr-subscribers-backend-risc-v Author: Philip Reames (preames) ChangesNoticed this while going to rewrite the load case as a DAG combine. I don't have a test case which demonstrates this leading to a miscompile, but it seems like it could be possible. Full diff: https://github.com/llvm/llvm-project/pull/150052.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
index 25817b6d2707f..878401ef4063f 100644
--- a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
@@ -232,6 +232,7 @@ bool RISCVTargetLowering::lowerInterleavedLoad(
Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_load,
{VTy, BasePtr->getType(), Stride->getType()},
{BasePtr, Stride, Mask, VL});
+ Alignment = commonAlignment(Alignment, Indices[0] * ScalarSizeInBytes);
CI->addParamAttr(0,
Attribute::getWithAlignment(CI->getContext(), Alignment));
Shuffles[0]->replaceAllUsesWith(CI);
@@ -303,8 +304,9 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
Intrinsic::experimental_vp_strided_store,
{Data->getType(), BasePtr->getType(), Stride->getType()},
{Data, BasePtr, Stride, Mask, VL});
+ Align Alignment = commonAlignment(SI->getAlign(), Index * ScalarSizeInBytes);
CI->addParamAttr(
- 1, Attribute::getWithAlignment(CI->getContext(), SI->getAlign()));
+ 1, Attribute::getWithAlignment(CI->getContext(), Alignment));
return true;
}
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You can test this locally with the following command:git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVInterleavedAccess.cppView the diff from clang-format here.diff --git a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
index 878401ef4..513dbf2ae 100644
--- a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
@@ -304,9 +304,10 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
Intrinsic::experimental_vp_strided_store,
{Data->getType(), BasePtr->getType(), Stride->getType()},
{Data, BasePtr, Stride, Mask, VL});
- Align Alignment = commonAlignment(SI->getAlign(), Index * ScalarSizeInBytes);
- CI->addParamAttr(
- 1, Attribute::getWithAlignment(CI->getContext(), Alignment));
+ Align Alignment =
+ commonAlignment(SI->getAlign(), Index * ScalarSizeInBytes);
+ CI->addParamAttr(1,
+ Attribute::getWithAlignment(CI->getContext(), Alignment));
return true;
}
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Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/27351 Here is the relevant piece of the build log for the reference |
mahesh-attarde
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Jul 28, 2025
…0052) Noticed this while going to rewrite the load case as a DAG combine. I don't have a test case which demonstrates this leading to a miscompile, but it seems like it could be possible.
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Noticed this while going to rewrite the load case as a DAG combine. I don't have a test case which demonstrates this leading to a miscompile, but it seems like it could be possible.