[TableGen] Add some -time-phases support in CodeGenRegisters

[jayfoad]

No description provided.

[llvmbot]

@llvm/pr-subscribers-tablegen

Author: Jay Foad (jayfoad)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/149309.diff

2 Files Affected:

• (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+10-1)
• (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+2)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 28b542f09e8c0..1730139ec0712 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -30,6 +30,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TGTimer.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
@@ -1130,7 +1131,7 @@ CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank,
 
 CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records,
                                const CodeGenHwModes &Modes)
-    : CGH(Modes) {
+    : Records(Records), CGH(Modes) {
   // Configure register Sets to understand register classes and tuples.
   Sets.addFieldExpander("RegisterClass", "MemberList");
   Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
@@ -2202,7 +2203,9 @@ void CodeGenRegBank::computeDerivedInfo() {
 
   // Compute a weight for each register unit created during getSubRegs.
   // This may create adopted register units (with unit # >= NumNativeRegUnits).
+  Records.getTimer().startTimer("Compute reg unit weights");
   computeRegUnitWeights();
+  Records.getTimer().stopTimer();
 
   // Compute a unique set of RegUnitSets. One for each RegClass and inferred
   // supersets for the union of overlapping sets.
@@ -2450,6 +2453,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() {
   // added.
   auto FirstNewRC = std::prev(RegClasses.end());
 
+  Records.getTimer().startTimer("Compute inferred register classes");
+
   // Visit all register classes, including the ones being added by the loop.
   // Watch out for iterator invalidation here.
   for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
@@ -2481,6 +2486,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() {
     }
   }
 
+  Records.getTimer().startTimer("Extend super-register classes");
+
   // Compute the transitive closure for super-register classes.
   //
   // By iterating over sub-register indices in topological order, we only ever
@@ -2491,6 +2498,8 @@ void CodeGenRegBank::computeInferredRegisterClasses() {
     for (CodeGenRegisterClass &SubRC : RegClasses)
       SubRC.extendSuperRegClasses(SubIdx);
   }
+
+  Records.getTimer().stopTimer();
 }
 
 /// getRegisterClassForRegister - Find the register class that contains the
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 5e6fff0f775ea..81aa663b8f11e 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -607,6 +607,8 @@ typedef SmallVector<unsigned, 16> TopoSigId;
 // CodeGenRegBank - Represent a target's registers and the relations between
 // them.
 class CodeGenRegBank {
+  const RecordKeeper &Records;
+
   SetTheory Sets;
 
   const CodeGenHwModes &CGH;

[nvjle]

LGTM, thanks!

FWIW, below are improvements on the downstream back-end mentioned in 149122 (before and after 149122). And as you mentioned, there is more low-hanging fruit.
===-------------------------------------------------------------------------===
                             TableGen Phase Timing
===-------------------------------------------------------------------------===
  Total Execution Time: 1.5125 seconds (1.5126 wall clock)

   ---User Time---   --System Time--   --User+System--   ---Wall Time---  --- Name ---
   0.9544 ( 67.7%)   0.0901 ( 88.1%)   1.0445 ( 69.1%)   1.0446 ( 69.1%)  Parse, build records
   0.3278 ( 23.2%)   0.0079 (  7.8%)   0.3357 ( 22.2%)   0.3357 ( 22.2%)  Print target registers
   0.0394 (  2.8%)   0.0000 (  0.0%)   0.0394 (  2.6%)   0.0394 (  2.6%)  Compute reg unit weights
   0.0315 (  2.2%)   0.0000 (  0.0%)   0.0315 (  2.1%)   0.0315 (  2.1%)  Compute inferred register classes
   0.0263 (  1.9%)   0.0000 (  0.0%)   0.0263 (  1.7%)   0.0263 (  1.7%)  Print MC registers
   0.0184 (  1.3%)   0.0002 (  0.2%)   0.0186 (  1.2%)   0.0186 (  1.2%)  Extend super-register classes
   0.0113 (  0.8%)   0.0000 (  0.0%)   0.0113 (  0.7%)   0.0113 (  0.7%)  Print enums
   0.0009 (  0.1%)   0.0041 (  4.0%)   0.0050 (  0.3%)   0.0050 (  0.3%)  Write output
   0.0001 (  0.0%)   0.0000 (  0.0%)   0.0001 (  0.0%)   0.0001 (  0.0%)  Print header fragment
   1.4102 (100.0%)   0.1023 (100.0%)   1.5125 (100.0%)   1.5126 (100.0%)  Total

===-------------------------------------------------------------------------===
                             TableGen Phase Timing
===-------------------------------------------------------------------------===
  Total Execution Time: 1.4949 seconds (1.4950 wall clock)

   ---User Time---   --System Time--   --User+System--   ---Wall Time---  --- Name ---
   0.9558 ( 68.0%)   0.0810 ( 90.8%)   1.0368 ( 69.4%)   1.0369 ( 69.4%)  Parse, build records
   0.3238 ( 23.0%)   0.0079 (  8.8%)   0.3316 ( 22.2%)   0.3316 ( 22.2%)  Print target registers
   0.0380 (  2.7%)   0.0001 (  0.2%)   0.0381 (  2.6%)   0.0381 (  2.6%)  Compute reg unit weights
   0.0280 (  2.0%)   0.0000 (  0.0%)   0.0280 (  1.9%)   0.0280 (  1.9%)  Compute inferred register classes
   0.0267 (  1.9%)   0.0000 (  0.0%)   0.0267 (  1.8%)   0.0267 (  1.8%)  Print MC registers
   0.0175 (  1.2%)   0.0001 (  0.1%)   0.0176 (  1.2%)   0.0176 (  1.2%)  Extend super-register classes
   0.0111 (  0.8%)   0.0000 (  0.0%)   0.0111 (  0.7%)   0.0111 (  0.7%)  Print enums
   0.0048 (  0.3%)   0.0000 (  0.1%)   0.0048 (  0.3%)   0.0048 (  0.3%)  Write output
   0.0001 (  0.0%)   0.0000 (  0.0%)   0.0001 (  0.0%)   0.0001 (  0.0%)  Print header fragment
   1.4058 (100.0%)   0.0892 (100.0%)   1.4949 (100.0%)   1.4950 (100.0%)  Total