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[AMDGPU] Simplify SIInstrInfo::isLegalToSwap. NFC. #149058

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Merged
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Jul 25, 2025
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[AMDGPU] Simplify SIInstrInfo::isLegalToSwap. NFC. #149058

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44 changes: 21 additions & 23 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2803,49 +2803,47 @@ static MachineInstr *swapImmOperands(MachineInstr &MI,
}

bool SIInstrInfo::isLegalToSwap(const MachineInstr &MI, unsigned OpIdx0,
const MachineOperand *MO0, unsigned OpIdx1,
const MachineOperand *MO1) const {
unsigned OpIdx1) const {
const MCInstrDesc &InstDesc = MI.getDesc();
const MCOperandInfo &OpInfo0 = InstDesc.operands()[OpIdx0];
const MCOperandInfo &OpInfo1 = InstDesc.operands()[OpIdx1];
const TargetRegisterClass *DefinedRC1 =
OpInfo1.RegClass != -1 ? RI.getRegClass(OpInfo1.RegClass) : nullptr;
const TargetRegisterClass *DefinedRC0 =
OpInfo1.RegClass != -1 ? RI.getRegClass(OpInfo0.RegClass) : nullptr;

unsigned Opc = MI.getOpcode();
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);

const MachineOperand &MO0 = MI.getOperand(OpIdx0);
const MachineOperand &MO1 = MI.getOperand(OpIdx1);

// Swap doesn't breach constant bus or literal limits
// It may move literal to position other than src0, this is not allowed
// pre-gfx10 However, most test cases need literals in Src0 for VOP
// FIXME: After gfx9, literal can be in place other than Src0
if (isVALU(MI)) {
if ((int)OpIdx0 == Src0Idx && !MO0->isReg() &&
!isInlineConstant(*MO0, OpInfo1))
if ((int)OpIdx0 == Src0Idx && !MO0.isReg() &&
!isInlineConstant(MO0, OpInfo1))
return false;
if ((int)OpIdx1 == Src0Idx && !MO1->isReg() &&
!isInlineConstant(*MO1, OpInfo0))
if ((int)OpIdx1 == Src0Idx && !MO1.isReg() &&
!isInlineConstant(MO1, OpInfo0))
return false;
}

if ((int)OpIdx1 != Src0Idx && MO0->isReg()) {
if (!DefinedRC1)
if ((int)OpIdx1 != Src0Idx && MO0.isReg()) {
if (OpInfo1.RegClass == -1)
return OpInfo1.OperandType == MCOI::OPERAND_UNKNOWN;
return isLegalRegOperand(MI, OpIdx1, *MO0) &&
(!MO1->isReg() || isLegalRegOperand(MI, OpIdx0, *MO1));
return isLegalRegOperand(MI, OpIdx1, MO0) &&
(!MO1.isReg() || isLegalRegOperand(MI, OpIdx0, MO1));
}
if ((int)OpIdx0 != Src0Idx && MO1->isReg()) {
if (!DefinedRC0)
if ((int)OpIdx0 != Src0Idx && MO1.isReg()) {
if (OpInfo0.RegClass == -1)
return OpInfo0.OperandType == MCOI::OPERAND_UNKNOWN;
return (!MO0->isReg() || isLegalRegOperand(MI, OpIdx1, *MO0)) &&
isLegalRegOperand(MI, OpIdx0, *MO1);
return (!MO0.isReg() || isLegalRegOperand(MI, OpIdx1, MO0)) &&
isLegalRegOperand(MI, OpIdx0, MO1);
}

// No need to check 64-bit literals since swapping does not bring new
// 64-bit literals into current instruction to fold to 32-bit

return isImmOperandLegal(MI, OpIdx1, *MO0);
return isImmOperandLegal(MI, OpIdx1, MO0);
}

MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Expand All @@ -2867,12 +2865,12 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices");

MachineOperand &Src0 = MI.getOperand(Src0Idx);
MachineOperand &Src1 = MI.getOperand(Src1Idx);
if (!isLegalToSwap(MI, Src0Idx, &Src0, Src1Idx, &Src1)) {
if (!isLegalToSwap(MI, Src0Idx, Src1Idx))
return nullptr;
}

MachineInstr *CommutedMI = nullptr;
MachineOperand &Src0 = MI.getOperand(Src0Idx);
MachineOperand &Src1 = MI.getOperand(Src1Idx);
if (Src0.isReg() && Src1.isReg()) {
// Be sure to copy the source modifiers to the right place.
CommutedMI =
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -196,8 +196,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
AMDGPU::OpName Src0OpName, MachineOperand &Src1,
AMDGPU::OpName Src1OpName) const;
bool isLegalToSwap(const MachineInstr &MI, unsigned fromIdx,
const MachineOperand *fromMO, unsigned toIdx,
const MachineOperand *toMO) const;
unsigned toIdx) const;
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned OpIdx0,
unsigned OpIdx1) const override;
Expand Down
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