[NFC] Correct typo: invertion -> inversion #147995
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llvmbot
added
llvm:globalisel
backend:NVPTX
llvm:SelectionDAG
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@llvm/pr-subscribers-backend-nvptx @llvm/pr-subscribers-llvm-selectiondag Author: Fraser Cormack (frasercrmck) ChangesFull diff: https://github.com/llvm/llvm-project/pull/147995.diff 3 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index cdf192f9e7e3a..11b3ac82e5136 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9272,7 +9272,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
APInt QNaNBitMask =
APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
auto SignBitC = MIRBuilder.buildConstant(IntTy, SignBit);
auto ValueMaskC = MIRBuilder.buildConstant(IntTy, ValueMask);
@@ -9400,7 +9400,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, Sign);
else if (PartialCheck == fcPosNormal) {
auto PosSign = MIRBuilder.buildXor(
- DstTy, Sign, MIRBuilder.buildConstant(DstTy, InvertionMask));
+ DstTy, Sign, MIRBuilder.buildConstant(DstTy, InversionMask));
NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, PosSign);
}
appendToRes(NormalRes);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b90c80002151f..4f251917ab3ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9053,14 +9053,14 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
APInt QNaNBitMask =
APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
SDValue ValueMaskV = DAG.getConstant(ValueMask, DL, IntVT);
SDValue SignBitV = DAG.getConstant(SignBit, DL, IntVT);
SDValue ExpMaskV = DAG.getConstant(ExpMask, DL, IntVT);
SDValue ZeroV = DAG.getConstant(0, DL, IntVT);
SDValue InfV = DAG.getConstant(Inf, DL, IntVT);
- SDValue ResultInvertionMask = DAG.getConstant(InvertionMask, DL, ResultVT);
+ SDValue ResultInversionMask = DAG.getConstant(InversionMask, DL, ResultVT);
SDValue Res;
const auto appendResult = [&](SDValue PartialRes) {
@@ -9204,7 +9204,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
else if (PartialCheck == fcPosNormal) {
SDValue PosSignV =
- DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInvertionMask);
+ DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInversionMask);
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, PosSignV);
}
if (IsF80)
@@ -9216,7 +9216,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
if (!Res)
return DAG.getConstant(IsInverted, DL, ResultVT);
if (IsInverted)
- Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInvertionMask);
+ Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInversionMask);
return Res;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 441ddeeb7d667..cebe1d19d05a3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -2738,7 +2738,7 @@ def : Pat<(brcond i32:$a, bb:$target),
// SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
// conditional branch if the target block is the next block so that the code
-// can fall through to the target block. The invertion is done by 'xor
+// can fall through to the target block. The inversion is done by 'xor
// condition, 1', which will be translated to (setne condition, -1). Since ptx
// supports '@!pred bra target', we should use it.
def : Pat<(brcond (i1 (setne i1:$a, -1)), bb:$target),
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@llvm/pr-subscribers-llvm-globalisel Author: Fraser Cormack (frasercrmck) ChangesFull diff: https://github.com/llvm/llvm-project/pull/147995.diff 3 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index cdf192f9e7e3a..11b3ac82e5136 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9272,7 +9272,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
APInt QNaNBitMask =
APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(DstTy.getScalarSizeInBits());
auto SignBitC = MIRBuilder.buildConstant(IntTy, SignBit);
auto ValueMaskC = MIRBuilder.buildConstant(IntTy, ValueMask);
@@ -9400,7 +9400,7 @@ LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, Sign);
else if (PartialCheck == fcPosNormal) {
auto PosSign = MIRBuilder.buildXor(
- DstTy, Sign, MIRBuilder.buildConstant(DstTy, InvertionMask));
+ DstTy, Sign, MIRBuilder.buildConstant(DstTy, InversionMask));
NormalRes = MIRBuilder.buildAnd(DstTy, NormalRes, PosSign);
}
appendToRes(NormalRes);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b90c80002151f..4f251917ab3ea 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9053,14 +9053,14 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
APInt AllOneMantissa = APFloat::getLargest(Semantics).bitcastToAPInt() & ~Inf;
APInt QNaNBitMask =
APInt::getOneBitSet(BitSize, AllOneMantissa.getActiveBits() - 1);
- APInt InvertionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
+ APInt InversionMask = APInt::getAllOnes(ResultVT.getScalarSizeInBits());
SDValue ValueMaskV = DAG.getConstant(ValueMask, DL, IntVT);
SDValue SignBitV = DAG.getConstant(SignBit, DL, IntVT);
SDValue ExpMaskV = DAG.getConstant(ExpMask, DL, IntVT);
SDValue ZeroV = DAG.getConstant(0, DL, IntVT);
SDValue InfV = DAG.getConstant(Inf, DL, IntVT);
- SDValue ResultInvertionMask = DAG.getConstant(InvertionMask, DL, ResultVT);
+ SDValue ResultInversionMask = DAG.getConstant(InversionMask, DL, ResultVT);
SDValue Res;
const auto appendResult = [&](SDValue PartialRes) {
@@ -9204,7 +9204,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, SignV);
else if (PartialCheck == fcPosNormal) {
SDValue PosSignV =
- DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInvertionMask);
+ DAG.getNode(ISD::XOR, DL, ResultVT, SignV, ResultInversionMask);
PartialRes = DAG.getNode(ISD::AND, DL, ResultVT, PartialRes, PosSignV);
}
if (IsF80)
@@ -9216,7 +9216,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
if (!Res)
return DAG.getConstant(IsInverted, DL, ResultVT);
if (IsInverted)
- Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInvertionMask);
+ Res = DAG.getNode(ISD::XOR, DL, ResultVT, Res, ResultInversionMask);
return Res;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 441ddeeb7d667..cebe1d19d05a3 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -2738,7 +2738,7 @@ def : Pat<(brcond i32:$a, bb:$target),
// SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
// conditional branch if the target block is the next block so that the code
-// can fall through to the target block. The invertion is done by 'xor
+// can fall through to the target block. The inversion is done by 'xor
// condition, 1', which will be translated to (setne condition, -1). Since ptx
// supports '@!pred bra target', we should use it.
def : Pat<(brcond (i1 (setne i1:$a, -1)), bb:$target),
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arsenm
approved these changes
Jul 10, 2025
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