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[RISCV] Fold (add (srl x, n), (srl x, n)) into (srl x, n-1) #144507

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bjope
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@bjope bjope commented Jun 17, 2025

This patch adds a new fold that will turn
(add (srl x, n), (srl x, n))
into
(srl x, n-1)
when bit n-1 is known to be zero in x.

This could perhaps be moved to generic DAGCombiner in the future, but this patch adds it as a RISCV specific combine. For RISCV it typically trigger for DAG nodes like this that may be created by the legalizer:
t1: i32 = srl RISCVISD::READ_VLENB:i32, Constant:i32<2>
t2: i32 = add t1, t1

Got the idea when working on a solution for #141034, as it may avoid some regressions otherwise caused by the fix being prepared for that issue.

This patch adds a new fold that will turn
  (add (srl x, n), (srl x, n))
into
  (srl x, n-1)
when bit n-1 is known to be zero in x.

This could perhaps be moved to generic DAGCombiner in the
future, but this patch adds it as a RISCV specific combine.
For RISCV it typically trigger for DAG nodes like this that
may be created by the legalizer:
  t1: i32 = srl RISCVISD::READ_VLENB:i32, Constant:i32<2>
  t2: i32 = add t1, t1

Got the idea when working on a solution for #141034, as it
may avoid some regressions otherwise caused by the fix being
prepared for that issue.
@bjope bjope requested review from preames, lukel97 and topperc June 17, 2025 11:20
@@ -15240,12 +15240,42 @@ static SDValue combineAddOfBooleanXor(SDNode *N, SelectionDAG &DAG) {
N0.getOperand(0));
}

// Try to turn (add (srl x, n), (srl x, n)) into (srl x, n-1).
//
// This combine could perhaps be moved to DAGCombiner. For RISCV this kind of
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RISCV should be spelled RISC-V in comments. It's a trademark.

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topperc commented Jun 17, 2025

I may have an alternate proposal for this patch. Investigating.

topperc added a commit to topperc/llvm-project that referenced this pull request Jun 17, 2025
… (C0 + C1)) in getNode.

This is an alternative to the DAGCombine proposed in llvm#144507.
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topperc commented Jun 17, 2025

I may have an alternate proposal for this patch. Investigating.

My alternate proposal #144565 which covers the READ_VLENB cases.

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bjope commented Jun 17, 2025

I may have an alternate proposal for this patch. Investigating.

My alternate proposal #144565 which covers the READ_VLENB cases.

Thanks! That seems like a better solution. I'll abandon this.

@bjope bjope closed this Jun 17, 2025
topperc added a commit that referenced this pull request Jun 18, 2025
…ale * (C0 + C1)) in getNode. (#144565)

We already have shl/mul vscale related folds in getNode.

This is an alternative to the DAGCombine proposed in #144507.
fschlimb pushed a commit to fschlimb/llvm-project that referenced this pull request Jun 18, 2025
…ale * (C0 + C1)) in getNode. (llvm#144565)

We already have shl/mul vscale related folds in getNode.

This is an alternative to the DAGCombine proposed in llvm#144507.
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2 participants