Skip to content

[acc] acc.loop verifier now requires parallelism determination flag #143720

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Jun 11, 2025
Merged

[acc] acc.loop verifier now requires parallelism determination flag #143720

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
f04736c
[acc] acc.loop verifier now requires parallelism determination flag
Jun 11, 2025
9d291ef
Fix format
Jun 11, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
35 changes: 29 additions & 6 deletions mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2461,10 +2461,34 @@ LogicalResult acc::LoopOp::verify() {
if (hasDuplicateDeviceTypes(getAuto_(), deviceTypes) ||
hasDuplicateDeviceTypes(getIndependent(), deviceTypes) ||
hasDuplicateDeviceTypes(getSeq(), deviceTypes)) {
return emitError() << "only one of \"" << acc::LoopOp::getAutoAttrStrName()
<< "\", " << getIndependentAttrName() << ", "
<< getSeqAttrName()
<< " can be present at the same time";
return emitError() << "only one of auto, independent, seq can be present "
"at the same time";
}

// Check that at least one of auto, independent, or seq is present
// for the device-independent default clauses.
auto hasDeviceNone = [](mlir::acc::DeviceTypeAttr attr) -> bool {
return attr.getValue() == mlir::acc::DeviceType::None;
};
bool hasDefaultSeq =
getSeqAttr()
? llvm::any_of(getSeqAttr().getAsRange<mlir::acc::DeviceTypeAttr>(),
hasDeviceNone)
: false;
bool hasDefaultIndependent =
getIndependentAttr()
? llvm::any_of(
getIndependentAttr().getAsRange<mlir::acc::DeviceTypeAttr>(),
hasDeviceNone)
: false;
bool hasDefaultAuto =
getAuto_Attr()
? llvm::any_of(getAuto_Attr().getAsRange<mlir::acc::DeviceTypeAttr>(),
hasDeviceNone)
: false;
if (!hasDefaultSeq && !hasDefaultIndependent && !hasDefaultAuto) {
return emitError()
<< "at least one of auto, independent, seq must be present";
}

// Gang, worker and vector are incompatible with seq.
Expand All @@ -2482,8 +2506,7 @@ LogicalResult acc::LoopOp::verify() {
deviceTypeAttr.getValue()) ||
getGangValue(mlir::acc::GangArgType::Static,
deviceTypeAttr.getValue()))
return emitError()
<< "gang, worker or vector cannot appear with the seq attr";
return emitError() << "gang, worker or vector cannot appear with seq";
}
}

Expand Down
4 changes: 2 additions & 2 deletions mlir/test/Dialect/OpenACC/canonicalize.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -116,10 +116,10 @@ func.func @testhostdataop(%a: memref<f32>, %ifCond: i1) -> () {
acc.host_data dataOperands(%0 : memref<f32>) if(%false) {
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes { inclusiveUpperbound = array<i1: true> }
} attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes { inclusiveUpperbound = array<i1: true> }
} attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}
acc.terminator
}
return
Expand Down
28 changes: 14 additions & 14 deletions mlir/test/Dialect/OpenACC/invalid.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -12,7 +12,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -22,7 +22,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -32,7 +32,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -42,7 +42,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -52,7 +52,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -62,7 +62,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
// expected-error@+1 {{gang, worker or vector cannot appear with seq}}
acc.loop {
"test.openacc_dummy_op"() : () -> ()
acc.yield
Expand All @@ -72,7 +72,7 @@ acc.loop {

// expected-error@+1 {{expected non-empty body.}}
acc.loop {
}
} attributes {independent = [#acc.device_type<none>]}

// -----

Expand All @@ -99,7 +99,7 @@ acc.loop {

%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error@+1 {{only one of "auto", "independent", "seq" can be present at the same time}}
// expected-error@+1 {{only one of auto, independent, seq can be present at the same time}}
acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes {auto_ = [#acc.device_type<none>], seq = [#acc.device_type<none>], inclusiveUpperbound = array<i1: true>}
Expand Down Expand Up @@ -168,7 +168,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32){
// expected-error@+1 {{'acc.init' op cannot be nested in a compute operation}}
acc.init
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
} attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}

// -----

Expand All @@ -186,7 +186,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
// expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
} attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}

// -----

Expand All @@ -198,7 +198,7 @@ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.shutdown
}) : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
} attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}

// -----

Expand Down Expand Up @@ -797,7 +797,7 @@ func.func @acc_loop_container() {
scf.yield
}
acc.yield
} attributes { collapse = [2], collapseDeviceType = [#acc.device_type<none>] }
} attributes { collapse = [2], collapseDeviceType = [#acc.device_type<none>], independent = [#acc.device_type<none>]}
return
}

Expand All @@ -816,6 +816,6 @@ func.func @acc_loop_container() {
scf.yield
}
acc.yield
} attributes { collapse = [3], collapseDeviceType = [#acc.device_type<none>] }
} attributes { collapse = [3], collapseDeviceType = [#acc.device_type<none>], independent = [#acc.device_type<none>]}
return
}
16 changes: 8 additions & 8 deletions mlir/test/Dialect/OpenACC/legalize-data.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ func.func @test(%a: memref<10xf32>) {
acc.loop control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%ci = memref.load %a[%i] : memref<10xf32>
acc.yield
}
} attributes {independent = [#acc.device_type<none>]}
acc.yield
}
return
Expand All @@ -109,7 +109,7 @@ func.func @test(%a: memref<10xf32>) {
// CHECK: acc.loop control(%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
// DEVICE: %{{.*}} = memref.load %[[CREATE:.*]][%[[I]]] : memref<10xf32>
// CHECK: acc.yield
// CHECK: }
// CHECK: } attributes {independent = [#acc.device_type<none>]}
// CHECK: acc.yield
// CHECK: }

Expand All @@ -134,7 +134,7 @@ func.func @test(%a: memref<10xf32>) {
acc.loop control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%ci = memref.load %a[%i] : memref<10xf32>
acc.yield
}
} attributes {independent = [#acc.device_type<none>]}
acc.yield
}
return
Expand All @@ -147,7 +147,7 @@ func.func @test(%a: memref<10xf32>) {
// CHECK: acc.loop control(%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
// DEVICE: %{{.*}} = memref.load %[[PRIVATE:.*]][%[[I]]] : memref<10xf32>
// CHECK: acc.yield
// CHECK: }
// CHECK: } attributes {independent = [#acc.device_type<none>]}
// CHECK: acc.yield
// CHECK: }

Expand All @@ -172,7 +172,7 @@ func.func @test(%a: memref<10xf32>) {
acc.loop private(@privatization_memref_10_f32 -> %p1 : memref<10xf32>) control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%ci = memref.load %a[%i] : memref<10xf32>
acc.yield
}
} attributes {independent = [#acc.device_type<none>]}
acc.yield
}
return
Expand All @@ -185,7 +185,7 @@ func.func @test(%a: memref<10xf32>) {
// CHECK: acc.loop private(@privatization_memref_10_f32 -> %[[PRIVATE]] : memref<10xf32>) control(%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
// DEVICE: %{{.*}} = memref.load %[[PRIVATE:.*]][%[[I]]] : memref<10xf32>
// CHECK: acc.yield
// CHECK: }
// CHECK: } attributes {independent = [#acc.device_type<none>]}
// CHECK: acc.yield
// CHECK: }

Expand All @@ -210,7 +210,7 @@ func.func @test(%a: memref<10xf32>) {
acc.loop control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%ci = memref.load %a[%i] : memref<10xf32>
acc.yield
}
} attributes {seq = [#acc.device_type<none>]}
acc.yield
}
return
Expand All @@ -223,7 +223,7 @@ func.func @test(%a: memref<10xf32>) {
// CHECK: acc.loop control(%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
// DEVICE: %{{.*}} = memref.load %[[PRIVATE:.*]][%[[I]]] : memref<10xf32>
// CHECK: acc.yield
// CHECK: }
// CHECK: } attributes {seq = [#acc.device_type<none>]}
// CHECK: acc.yield
// CHECK: }

Expand Down
Loading
Loading