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[AArch64] Change IssueWidth to 6 in AArch64SchedNeoverseV2.td #142565

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Merged
merged 1 commit into from
Jun 9, 2025
+1,413 −1,409
Merged

[AArch64] Change IssueWidth to 6 in AArch64SchedNeoverseV2.td #142565

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4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,9 @@
//===----------------------------------------------------------------------===//

def NeoverseV2Model : SchedMachineModel {
let IssueWidth = 16; // Micro-ops dispatched at a time.
let IssueWidth = 6; // This value comes from the decode bandwidth
// and empirical measurements showed that a
// lower value is better.
let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
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Original file line number Diff line number Diff line change
Expand Up @@ -2536,14 +2536,14 @@ drps
# CHECK-NEXT: 1 2 0.50 bics x3, xzr, x3, lsl #1
# CHECK-NEXT: 1 2 0.50 tst w3, w7, lsl #31
# CHECK-NEXT: 1 2 0.50 tst x2, x20, asr #2
# CHECK-NEXT: 1 0 0.06 mov x3, x6
# CHECK-NEXT: 1 0 0.06 mov x3, xzr
# CHECK-NEXT: 1 0 0.06 mov wzr, w2
# CHECK-NEXT: 1 0 0.06 mov w3, w5
# CHECK-NEXT: 1 0 0.17 mov x3, x6
# CHECK-NEXT: 1 0 0.17 mov x3, xzr
# CHECK-NEXT: 1 0 0.17 mov wzr, w2
# CHECK-NEXT: 1 0 0.17 mov w3, w5
# CHECK-NEXT: 1 1 0.17 movz w2, #0, lsl #16
# CHECK-NEXT: 1 1 0.17 mov w2, #-1235
# CHECK-NEXT: 1 1 0.17 mov x2, #5299989643264
# CHECK-NEXT: 1 0 0.06 mov x2, #0
# CHECK-NEXT: 1 0 0.17 mov x2, #0
# CHECK-NEXT: 1 1 0.17 movk w3, #0
# CHECK-NEXT: 1 1 0.17 movz x4, #0, lsl #16
# CHECK-NEXT: 1 1 0.17 movk w5, #0, lsl #16
Expand Down
124 changes: 62 additions & 62 deletions llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -116,8 +116,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ldr b0, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -126,9 +126,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ldr b0, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [1] Code Region - FPR16-bit

Expand All @@ -137,7 +137,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -195,8 +195,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ldr h0, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -205,9 +205,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ldr h0, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [2] Code Region - FPR32-bit

Expand All @@ -216,7 +216,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -274,8 +274,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ldr s0, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -284,9 +284,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ldr s0, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [3] Code Region - FPR64-bit

Expand All @@ -295,7 +295,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -353,8 +353,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr d0, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr d0, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ldr d0, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -363,9 +363,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr d0, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ldr d0, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [4] Code Region - FPR128-bit

Expand All @@ -374,7 +374,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -432,8 +432,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr q0, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr q0, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ldr q0, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -442,9 +442,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr q0, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ldr q0, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [5] Code Region - SIMD64-bit-b

Expand All @@ -453,7 +453,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -511,8 +511,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ld1 { v0.8b }, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -521,9 +521,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ld1 { v0.8b }, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [6] Code Region - SIMD64-bit-h

Expand All @@ -532,7 +532,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -590,8 +590,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ld1 { v0.4h }, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -600,9 +600,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ld1 { v0.4h }, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [7] Code Region - SIMD64-bit-s

Expand All @@ -611,7 +611,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -669,8 +669,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ld1 { v0.2s }, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -679,9 +679,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ld1 { v0.2s }, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [8] Code Region - SIMD64-bit-d

Expand All @@ -690,7 +690,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 4.55
# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
Expand Down Expand Up @@ -748,8 +748,8 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK-NEXT: [3,0] .DeeeeeeE-R. ld1 { v0.1d }, [sp]
# CHECK-NEXT: [3,1] .D======eeER add z0.d, z0.d, z0.d

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -758,9 +758,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK-NEXT: 0. 4 1.0 1.0 1.3 ld1 { v0.1d }, [sp]
# CHECK-NEXT: 1. 4 7.0 0.0 0.0 add z0.d, z0.d, z0.d
# CHECK-NEXT: 4 4.0 0.5 0.6 <total>

# CHECK: [9] Code Region - insr

Expand All @@ -769,7 +769,7 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: Total Cycles: 803
# CHECK-NEXT: Total uOps: 300

# CHECK: Dispatch Width: 16
# CHECK: Dispatch Width: 6
# CHECK-NEXT: uOps Per Cycle: 0.37
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 1.0
Expand Down Expand Up @@ -825,10 +825,10 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [0,1] D======eeER . . . . . add z0.s, z0.s, z0.s
# CHECK-NEXT: [1,0] D========eeeeeeER . . . . insr z0.s, w0
# CHECK-NEXT: [1,1] D==============eeER . . . . add z0.s, z0.s, z0.s
# CHECK-NEXT: [2,0] D================eeeeeeER. . . insr z0.s, w0
# CHECK-NEXT: [2,1] D======================eeER . . add z0.s, z0.s, z0.s
# CHECK-NEXT: [3,0] D========================eeeeeeER . insr z0.s, w0
# CHECK-NEXT: [3,1] D==============================eeER add z0.s, z0.s, z0.s
# CHECK-NEXT: [2,0] .D===============eeeeeeER. . . insr z0.s, w0
# CHECK-NEXT: [2,1] .D=====================eeER . . add z0.s, z0.s, z0.s
# CHECK-NEXT: [3,0] .D=======================eeeeeeER . insr z0.s, w0
# CHECK-NEXT: [3,1] .D=============================eeER add z0.s, z0.s, z0.s

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand All @@ -837,6 +837,6 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 4 13.0 0.3 0.0 insr z0.s, w0
# CHECK-NEXT: 1. 4 19.0 0.0 0.0 add z0.s, z0.s, z0.s
# CHECK-NEXT: 4 16.0 0.1 0.0 <total>
# CHECK-NEXT: 0. 4 12.5 0.3 0.0 insr z0.s, w0
# CHECK-NEXT: 1. 4 18.5 0.0 0.0 add z0.s, z0.s, z0.s
# CHECK-NEXT: 4 15.5 0.1 0.0 <total>
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