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[InstCombine] Do not fold logical is_finite test #136851

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Merged
merged 2 commits into from
Apr 23, 2025
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[InstCombine] Do not fold logical is_finite test #136851

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7e531fd
[InstCombine] Add pre-commit tests. NFC.
dtcxzyw Apr 23, 2025
7cb989a
[InstCombine] Do not fold logical is_finite test
dtcxzyw Apr 23, 2025
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4 changes: 3 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1480,7 +1480,9 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS,
}
}

if (IsAnd && stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) {
// This transform is not valid for a logical select.
if (!IsLogicalSelect && IsAnd &&
stripSignOnlyFPOps(LHS0) == stripSignOnlyFPOps(RHS0)) {
// and (fcmp ord x, 0), (fcmp u* x, inf) -> fcmp o* x, inf
// and (fcmp ord x, 0), (fcmp u* fabs(x), inf) -> fcmp o* x, inf
if (Value *Left = matchIsFiniteTest(Builder, LHS, RHS))
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28 changes: 28 additions & 0 deletions llvm/test/Transforms/InstCombine/and-fcmp.ll
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Expand Up @@ -4990,6 +4990,34 @@ define i1 @clang_builtin_isnormal_inf_check_copysign(half %x, half %y) {
ret i1 %and
}

define i1 @clang_builtin_isnormal_inf_check_copysign_logical_select(half %x, half %y) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_copysign_logical_select(
; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.copysign.f16(half [[X:%.*]], half [[Y:%.*]])
; CHECK-NEXT: [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
; CHECK-NEXT: [[CMP:%.*]] = fcmp ueq half [[COPYSIGN_X]], 0xH7C00
; CHECK-NEXT: [[AND:%.*]] = select i1 [[ORD]], i1 [[CMP]], i1 false
; CHECK-NEXT: ret i1 [[AND]]
;
%copysign.x = call half @llvm.copysign.f16(half %x, half %y)
%ord = fcmp ord half %x, 0.0
%cmp = fcmp uge half %copysign.x, 0xH7C00
%and = select i1 %ord, i1 %cmp, i1 false
ret i1 %and
}

define i1 @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(half %x) {
; CHECK-LABEL: @clang_builtin_isnormal_inf_check_fabs_nnan_logical_select(
; CHECK-NEXT: [[COPYSIGN_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
; CHECK-NEXT: [[AND:%.*]] = fcmp oeq half [[COPYSIGN_X]], 0xH7C00
; CHECK-NEXT: ret i1 [[AND]]
;
%copysign.x = call nnan half @llvm.fabs.f16(half %x)
%ord = fcmp ord half %x, 0.0
%cmp = fcmp uge half %copysign.x, 0xH7C00
%and = select i1 %ord, i1 %cmp, i1 false
ret i1 %and
}

define i1 @isnormal_logical_select_0(half %x) {
; CHECK-LABEL: @isnormal_logical_select_0(
; CHECK-NEXT: [[FABS_X:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
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