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This patch partially reverts:

commit 5e1b0f9
Author: Kazu Hirata [email protected]
Date: Fri Apr 18 10:05:55 2025 -0700

to fix:

LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

under LLVM_ENABLE_EXPENSIVE_CHECKS.

This patch partially reverts:

  commit 5e1b0f9
  Author: Kazu Hirata <[email protected]>
  Date:   Fri Apr 18 10:05:55 2025 -0700

to fix:

  LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
  LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

under LLVM_ENABLE_EXPENSIVE_CHECKS.
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llvmbot commented Apr 21, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Kazu Hirata (kazutakahirata)

Changes

This patch partially reverts:

commit 5e1b0f9
Author: Kazu Hirata <[email protected]>
Date: Fri Apr 18 10:05:55 2025 -0700

to fix:

LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

under LLVM_ENABLE_EXPENSIVE_CHECKS.


Full diff: https://github.com/llvm/llvm-project/pull/136615.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp (+1-1)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 815715604bc96..87c1d2586cce5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -589,7 +589,7 @@ void PipelineSolver::populateReadyList(
   }
 
   if (UseCostHeur)
-    llvm::sort(ReadyList, llvm::less_second());
+    std::sort(ReadyList.begin(), ReadyList.end(), llvm::less_second());
 
   assert(ReadyList.size() == CurrSU.second.size());
 }

@kazutakahirata kazutakahirata merged commit 515564a into llvm:main Apr 21, 2025
10 of 13 checks passed
@kazutakahirata kazutakahirata deleted the amdgpu_stable_sort branch April 21, 2025 21:55
IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025
This patch partially reverts:

  commit 5e1b0f9
  Author: Kazu Hirata <[email protected]>
  Date:   Fri Apr 18 10:05:55 2025 -0700

to fix:

  LLVM :: CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
  LLVM :: CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

under LLVM_ENABLE_EXPENSIVE_CHECKS.
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3 participants