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[AMDGPU] Add sext_trunc in RegBankCombiner #131623

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Merged
merged 3 commits into from
Apr 14, 2025
Merged

[AMDGPU] Add sext_trunc in RegBankCombiner #131623

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9e689be
[AMDGPU] Add sext_trunc in RegBankCombiner
Pierre-vh Mar 17, 2025
5217b22
Add test
Pierre-vh Mar 24, 2025
2f2f6b7
Drop -verify-machineinstrs
Pierre-vh Mar 26, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUCombine.td
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Original file line number Diff line number Diff line change
Expand Up @@ -182,5 +182,5 @@ def AMDGPURegBankCombiner : GICombiner<
zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp,
identity_combines, redundant_and, constant_fold_cast_op,
cast_of_cast_combines]> {
cast_of_cast_combines, sext_trunc]> {
}
43 changes: 30 additions & 13 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
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@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s

---
name: trunc_sext_i32_i16
Expand Down Expand Up @@ -65,12 +66,20 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3

; GCN-LABEL: name: trunc_sext_v4i32_v4i16
; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>)
; PRELEGAL-LABEL: name: trunc_sext_v4i32_v4i16
; PRELEGAL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; PRELEGAL-NEXT: {{ $}}
; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16
; PRELEGAL-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>)
;
; RBCOMB-LABEL: name: trunc_sext_v4i32_v4i16
; RBCOMB: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; RBCOMB-NEXT: {{ $}}
; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[TRUNC]](<4 x s16>)
; RBCOMB-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<4 x s16>) = G_TRUNC %0
%2:_(<4 x s32>) = G_SEXT %1
Expand All @@ -84,12 +93,20 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1

; GCN-LABEL: name: trunc_sext_v4i16_v4i8
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>)
; PRELEGAL-LABEL: name: trunc_sext_v4i16_v4i8
; PRELEGAL: liveins: $vgpr0_vgpr1
; PRELEGAL-NEXT: {{ $}}
; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8
; PRELEGAL-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>)
;
; RBCOMB-LABEL: name: trunc_sext_v4i16_v4i8
; RBCOMB: liveins: $vgpr0_vgpr1
; RBCOMB-NEXT: {{ $}}
; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY]](<4 x s16>)
; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s16>) = G_SEXT [[TRUNC]](<4 x s8>)
; RBCOMB-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s8>) = G_TRUNC %0
%2:_(<4 x s16>) = G_SEXT %1
Expand Down
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