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AMDGPU: Replace ptr addrspace(3) undef in tests with poison #131049

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Merged
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Mar 13, 2025
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AMDGPU: Replace ptr addrspace(3) undef in tests with poison #131049

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
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Expand Up @@ -92,7 +92,7 @@ define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %o
}


@ptr = addrspace(3) global ptr addrspace(3) undef
@ptr = addrspace(3) global ptr addrspace(3) poison
@dst = addrspace(3) global [16383 x i32] undef

; FUNC-LABEL: {{^}}global_ptr:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
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Expand Up @@ -1619,7 +1619,7 @@ define amdgpu_ps void @dyn_extract_v8p3_s_s(<8 x ptr addrspace(3)> inreg %vec, i
; GFX11-NEXT: s_endpgm
entry:
%ext = extractelement <8 x ptr addrspace(3)> %vec, i32 %idx
store ptr addrspace(3) %ext, ptr addrspace(3) undef
store ptr addrspace(3) %ext, ptr addrspace(3) poison
ret void
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
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Expand Up @@ -229,7 +229,7 @@ define float @v_test_fmax_legacy_ule_f32_multi_use(float %a, float %b) {
%cmp = fcmp ogt float %a, %b
%val0 = select i1 %cmp, float %a, float %b
%val1 = zext i1 %cmp to i32
store i32 %val1, ptr addrspace(3) undef
store i32 %val1, ptr addrspace(3) poison
ret float %val0
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
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Expand Up @@ -212,7 +212,7 @@ define float @v_test_fmin_legacy_ule_f32_multi_use(float %a, float %b) {
%cmp = fcmp ule float %a, %b
%val0 = select i1 %cmp, float %a, float %b
%val1 = zext i1 %cmp to i32
store i32 %val1, ptr addrspace(3) undef
store i32 %val1, ptr addrspace(3) poison
ret float %val0
}

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44 changes: 22 additions & 22 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
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Expand Up @@ -1062,10 +1062,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32)
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32)
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32)
Expand All @@ -1075,10 +1075,10 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%load0 = load volatile i32, ptr addrspace(3) undef
%load1 = load volatile i32, ptr addrspace(3) undef
%load2 = load volatile i32, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
%load0 = load volatile i32, ptr addrspace(3) poison
%load1 = load volatile i32, ptr addrspace(3) poison
%load2 = load volatile i32, ptr addrspace(3) poison
%load3 = load volatile i32, ptr addrspace(3) poison

%insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
Expand All @@ -1097,10 +1097,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[DEF1]], [[LOAD]](s32), [[C]](s32)
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC]], [[LOAD1]](s32), [[C1]](s32)
; CHECK-NEXT: [[IVEC2:%[0-9]+]]:_(<3 x s32>) = G_INSERT_VECTOR_ELT [[IVEC1]], [[LOAD2]](s32), [[C2]](s32)
Expand All @@ -1110,10 +1110,10 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
; CHECK-NEXT: $vgpr3 = COPY [[LOAD3]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%load0 = load volatile float, ptr addrspace(3) undef
%load1 = load volatile float, ptr addrspace(3) undef
%load2 = load volatile float, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
%load0 = load volatile float, ptr addrspace(3) poison
%load1 = load volatile float, ptr addrspace(3) poison
%load2 = load volatile float, ptr addrspace(3) poison
%load3 = load volatile i32, ptr addrspace(3) poison

%insert.0 = insertelement <3 x float> poison, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
Expand All @@ -1137,19 +1137,19 @@ define void @void_func_sret_max_known_zero_bits(ptr addrspace(5) sret(i8) %arg0)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[LSHR]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: SI_RETURN
%arg0.int = ptrtoint ptr addrspace(5) %arg0 to i32

%lshr0 = lshr i32 %arg0.int, 16
%lshr1 = lshr i32 %arg0.int, 17
%lshr2 = lshr i32 %arg0.int, 18

store volatile i32 %lshr0, ptr addrspace(3) undef
store volatile i32 %lshr1, ptr addrspace(3) undef
store volatile i32 %lshr2, ptr addrspace(3) undef
store volatile i32 %lshr0, ptr addrspace(3) poison
store volatile i32 %lshr1, ptr addrspace(3) poison
store volatile i32 %lshr2, ptr addrspace(3) poison
ret void
}

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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
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Expand Up @@ -1239,10 +1239,10 @@ define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
; GCN-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) undef`, addrspace 3)
; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `ptr addrspace(3) poison`, addrspace 3)
; GCN-NEXT: S_ENDPGM 0
%val = call ptr addrspace(3) @external_p3_func_void()
store volatile ptr addrspace(3) %val, ptr addrspace(3) undef
store volatile ptr addrspace(3) %val, ptr addrspace(3) poison
ret void
}

Expand Down Expand Up @@ -1299,10 +1299,10 @@ define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) undef`, addrspace 3)
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `ptr addrspace(3) poison`, addrspace 3)
; GCN-NEXT: S_ENDPGM 0
%val = call <2 x ptr addrspace(3)> @external_v2p3_func_void()
store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) undef
store volatile <2 x ptr addrspace(3)> %val, ptr addrspace(3) poison
ret void
}

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36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
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Expand Up @@ -1699,13 +1699,13 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 }
; CHECK-NEXT: G_STORE [[LOAD2]](s8), [[DEF]](p1) :: (volatile store (s8) into `ptr addrspace(1) poison`, align 4, addrspace 1)
; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C1]](s64)
; CHECK-NEXT: G_STORE [[LOAD3]](s32), [[PTR_ADD3]](p1) :: (volatile store (s32) into `ptr addrspace(1) poison` + 4, addrspace 1)
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[DEF1]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: SI_RETURN
%arg0.load = load volatile { i8, i32 }, ptr addrspace(5) %arg0
%arg1.load = load volatile { i8, i32 }, ptr addrspace(5) %arg1
store volatile { i8, i32 } %arg0.load, ptr addrspace(1) poison
store volatile { i8, i32 } %arg1.load, ptr addrspace(1) poison
store volatile i32 %arg2, ptr addrspace(3) undef
store volatile i32 %arg2, ptr addrspace(3) poison
ret void
}

Expand Down Expand Up @@ -2540,18 +2540,18 @@ define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 {
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: SI_RETURN
%arg0.0 = extractelement <3 x float> %arg0, i32 0
%arg0.1 = extractelement <3 x float> %arg0, i32 1
%arg0.2 = extractelement <3 x float> %arg0, i32 2
store volatile float %arg0.0, ptr addrspace(3) undef
store volatile float %arg0.1, ptr addrspace(3) undef
store volatile float %arg0.2, ptr addrspace(3) undef
store volatile i32 %arg1, ptr addrspace(3) undef
store volatile float %arg0.0, ptr addrspace(3) poison
store volatile float %arg0.1, ptr addrspace(3) poison
store volatile float %arg0.2, ptr addrspace(3) poison
store volatile i32 %arg1, ptr addrspace(3) poison
ret void
}

Expand All @@ -2572,18 +2572,18 @@ define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 {
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C]](s32)
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C1]](s32)
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[C2]](s32)
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC1]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[EVEC2]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: G_STORE [[COPY3]](s32), [[DEF]](p3) :: (volatile store (s32) into `ptr addrspace(3) poison`, addrspace 3)
; CHECK-NEXT: SI_RETURN
%arg0.0 = extractelement <3 x i32> %arg0, i32 0
%arg0.1 = extractelement <3 x i32> %arg0, i32 1
%arg0.2 = extractelement <3 x i32> %arg0, i32 2
store volatile i32 %arg0.0, ptr addrspace(3) undef
store volatile i32 %arg0.1, ptr addrspace(3) undef
store volatile i32 %arg0.2, ptr addrspace(3) undef
store volatile i32 %arg1, ptr addrspace(3) undef
store volatile i32 %arg0.0, ptr addrspace(3) poison
store volatile i32 %arg0.1, ptr addrspace(3) poison
store volatile i32 %arg0.2, ptr addrspace(3) poison
store volatile i32 %arg1, ptr addrspace(3) poison
ret void
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/add.ll
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Expand Up @@ -1389,7 +1389,7 @@ define amdgpu_ps void @add_select_vop3(i32 inreg %s, i32 %v) {
; GFX12-NEXT: s_endpgm
%vcc = call i64 asm sideeffect "; def vcc", "={vcc}"()
%sub = add i32 %v, %s
store i32 %sub, ptr addrspace(3) undef
store i32 %sub, ptr addrspace(3) poison
call void asm sideeffect "; use vcc", "{vcc}"(i64 %vcc)
ret void
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
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Expand Up @@ -863,7 +863,7 @@ bb16: ; preds = %bb58, %bb14
%i34 = getelementptr inbounds [16 x half], ptr addrspace(1) null, i64 %i24, i64 14
%i36 = load volatile <2 x half>, ptr addrspace(1) %i34, align 4
%i43 = load volatile <2 x float>, ptr addrspace(3) null, align 8
%i46 = load volatile <2 x float>, ptr addrspace(3) undef, align 32
%i46 = load volatile <2 x float>, ptr addrspace(3) poison, align 32
fence syncscope("workgroup") acquire
br i1 %i11, label %bb58, label %bb51

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
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Expand Up @@ -31,7 +31,7 @@ bb:
br i1 %tmp3, label %bb4, label %bb5

bb4: ; preds = %bb
store volatile i32 4, ptr addrspace(3) undef
store volatile i32 4, ptr addrspace(3) poison
unreachable

bb5: ; preds = %bb
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
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Expand Up @@ -607,7 +607,7 @@ done:
; OPT-LABEL: @test_wrong_operand_local_small_offset_cmpxchg_i32(
; OPT: %in.gep = getelementptr i32, ptr addrspace(3) %in, i32 7
; OPT: br i1
; OPT: cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic
; OPT: cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic
define amdgpu_kernel void @test_wrong_operand_local_small_offset_cmpxchg_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
entry:
%out.gep = getelementptr ptr addrspace(3), ptr addrspace(3) %out, i32 999999
Expand All @@ -617,7 +617,7 @@ entry:
br i1 %tmp0, label %endif, label %if

if:
%tmp1.struct = cmpxchg ptr addrspace(3) undef, ptr addrspace(3) %in.gep, ptr addrspace(3) undef seq_cst monotonic
%tmp1.struct = cmpxchg ptr addrspace(3) poison, ptr addrspace(3) %in.gep, ptr addrspace(3) poison seq_cst monotonic
%tmp1 = extractvalue { ptr addrspace(3), i1 } %tmp1.struct, 0
br label %endif

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/concat_vectors.ll
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Expand Up @@ -313,7 +313,7 @@ define amdgpu_kernel void @concat_vector_crash2(ptr addrspace(1) %out, ptr addrs
; VI: ds_write_b128
define amdgpu_kernel void @build_vector_splat_concat_v8i16() {
entry:
store <8 x i16> zeroinitializer, ptr addrspace(3) undef, align 16
store <8 x i16> zeroinitializer, ptr addrspace(3) poison, align 16
store <8 x i16> zeroinitializer, ptr addrspace(3) null, align 16
ret void
}
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -66,12 +66,12 @@
define amdgpu_kernel void @divergent_if_endif(ptr addrspace(1) %out) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%load0 = load volatile i32, ptr addrspace(3) undef
%load0 = load volatile i32, ptr addrspace(3) poison
%cmp0 = icmp eq i32 %tid, 0
br i1 %cmp0, label %if, label %endif

if:
%load1 = load volatile i32, ptr addrspace(3) undef
%load1 = load volatile i32, ptr addrspace(3) poison
%val = add i32 %load0, %load1
br label %endif

Expand Down Expand Up @@ -145,7 +145,7 @@ entry:
loop:
%i = phi i32 [ %i.inc, %loop ], [ 0, %entry ]
%val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ]
%load1 = load volatile i32, ptr addrspace(3) undef
%load1 = load volatile i32, ptr addrspace(3) poison
%i.inc = add i32 %i, 1
%val.sub = sub i32 %val, %load1
%cmp1 = icmp ne i32 %i, 256
Expand Down Expand Up @@ -257,12 +257,12 @@ entry:
br i1 %cmp0, label %if, label %else

if:
%load1 = load volatile i32, ptr addrspace(3) undef
%load1 = load volatile i32, ptr addrspace(3) poison
%val0 = add i32 %load0, %load1
br label %endif

else:
%load2 = load volatile i32, ptr addrspace(3) undef
%load2 = load volatile i32, ptr addrspace(3) poison
%val1 = sub i32 %load0, %load2
br label %endif

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AMDGPU/fminnum.f64.ll
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Expand Up @@ -47,10 +47,10 @@ define amdgpu_kernel void @test_fmin_f64_ieee_flush([8 x i32], double %a, [8 x i
; GCN-NOT: [[RESULT]]
; GCN: ds_write_b64 v{{[0-9]+}}, [[RESULT]]
define amdgpu_ps void @test_fmin_f64_no_ieee() nounwind {
%a = load volatile double, ptr addrspace(3) undef
%b = load volatile double, ptr addrspace(3) undef
%a = load volatile double, ptr addrspace(3) poison
%b = load volatile double, ptr addrspace(3) poison
%val = call double @llvm.minnum.f64(double %a, double %b) #0
store volatile double %val, ptr addrspace(3) undef
store volatile double %val, ptr addrspace(3) poison
ret void
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-atomics.ll
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Expand Up @@ -180,7 +180,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
; G_GFX1030-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
store double %ret, ptr addrspace(3) undef
store double %ret, ptr addrspace(3) poison
ret void
}

Expand Down Expand Up @@ -417,7 +417,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
; G_GFX1030-NEXT: s_endpgm
main_body:
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
store double %ret, ptr addrspace(3) undef
store double %ret, ptr addrspace(3) poison
ret void
}

Expand Down
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